e9b3f3045d
being switched out may hold a reservation. The stwcx. will clear the reservation. This is architecturally recommended. The scenario this addresses is as follows: 1. Thread 1 performs a lwarx and as such holds a reservation. 2. Thread 1 gets switched out (before doing the matching stwcx.) and thread 2 is switched in. 3. Thread 2 performs a stwcx. to the same reservation granule. This will succeed because the processor has the reservation even though thread 2 didn't do the lwarx. Note that on some processors the address given the stwcx. is not checked. On these processors the mere condition of having a reservation would cause the stwcx. to succeed, irrespective of whether the addresses are the same. The dummy stwcx. is especially important for those processors.
191 lines
6.3 KiB
ArmAsm
191 lines
6.3 KiB
ArmAsm
/* $FreeBSD$ */
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/* $NetBSD: locore.S,v 1.24 2000/05/31 05:09:17 thorpej Exp $ */
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/*-
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* Copyright (C) 2001 Benno Rice
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.s"
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#include <sys/syscall.h>
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#include <machine/trap.h>
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#include <machine/param.h>
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#include <machine/sr.h>
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#include <machine/psl.h>
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#include <machine/asm.h>
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/*
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* void cpu_throw(struct thread *old, struct thread *new)
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*/
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ENTRY(cpu_throw)
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mr %r15, %r4
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b cpu_switchin
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/*
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* void cpu_switch(struct thread *old,
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* struct thread *new,
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* struct mutex *mtx);
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*
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* Switch to a new thread saving the current state in the old thread.
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*/
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ENTRY(cpu_switch)
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stw %r5,TD_LOCK(%r3) /* ULE: update old thread's lock */
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/* XXX needs to change for MP */
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lwz %r5,TD_PCB(%r3) /* Get the old thread's PCB ptr */
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mr %r12,%r2
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stmw %r12,PCB_CONTEXT(%r5) /* Save the non-volatile GP regs.
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These can now be used for scratch */
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mfcr %r16 /* Save the condition register */
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stw %r16,PCB_CR(%r5)
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mflr %r16 /* Save the link register */
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stw %r16,PCB_LR(%r5)
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mfsr %r16,USER_SR /* Save USER_SR for copyin/out */
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isync
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stw %r16,PCB_AIM_USR(%r5)
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stw %r1,PCB_SP(%r5) /* Save the stack pointer */
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mr %r14,%r3 /* Copy the old thread ptr... */
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mr %r15,%r4 /* and the new thread ptr in scratch */
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lwz %r6,PCB_FLAGS(%r5)
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/* Save FPU context if needed */
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andi. %r6, %r6, PCB_FPU
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beq .L1
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bl save_fpu
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.L1:
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lwz %r6,PCB_FLAGS(%r5)
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/* Save Altivec context if needed */
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andi. %r6, %r6, PCB_VEC
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beq .L2
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bl save_vec
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.L2:
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mr %r3,%r14 /* restore old thread ptr */
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bl pmap_deactivate /* Deactivate the current pmap */
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cpu_switchin:
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mfsprg %r7,0 /* Get the pcpu pointer */
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stw %r15,PC_CURTHREAD(%r7) /* Store new current thread */
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lwz %r17,TD_PCB(%r15) /* Store new current PCB */
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stw %r17,PC_CURPCB(%r7)
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mr %r3,%r15 /* Get new thread ptr */
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bl pmap_activate /* Activate the new address space */
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore FPU context if needed */
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andi. %r6, %r6, PCB_FPU
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beq .L3
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mr %r3,%r15 /* Pass curthread to enable_fpu */
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bl enable_fpu
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.L3:
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore Altivec context if needed */
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andi. %r6, %r6, PCB_VEC
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beq .L4
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mr %r3,%r15 /* Pass curthread to enable_vec */
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bl enable_vec
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/* thread to restore is in r3 */
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.L4:
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mr %r3,%r17 /* Recover PCB ptr */
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lmw %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */
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mr %r2,%r12
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lwz %r5,PCB_CR(%r3) /* Load the condition register */
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mtcr %r5
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lwz %r5,PCB_LR(%r3) /* Load the link register */
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mtlr %r5
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lwz %r5,PCB_AIM_USR(%r3) /* Load the USER_SR segment reg */
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mtsr USER_SR,%r5
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isync
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lwz %r1,PCB_SP(%r3) /* Load the stack pointer */
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/*
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* Perform a dummy stwcx. to clear any reservations we may have
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* inherited from the previous thread. It doesn't matter if the
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* stwcx succeeds or not. pcb_context[0] can be clobbered.
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*/
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stwcx. %r1, 0, %r3
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blr
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/*
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* savectx(pcb)
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* Update pcb, saving current processor state
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*/
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ENTRY(savectx)
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mr %r12,%r2
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stmw %r12,PCB_CONTEXT(%r3) /* Save the non-volatile GP regs */
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mfcr %r4 /* Save the condition register */
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stw %r4,PCB_CONTEXT(%r3)
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blr
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/*
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* fork_trampoline()
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* Set up the return from cpu_fork()
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*/
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ENTRY(fork_trampoline)
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lwz %r3,CF_FUNC(%r1)
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lwz %r4,CF_ARG0(%r1)
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lwz %r5,CF_ARG1(%r1)
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bl fork_exit
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addi %r1,%r1,CF_SIZE-FSP /* Allow 8 bytes in front of
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trapframe to simulate FRAME_SETUP
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does when allocating space for
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a frame pointer/saved LR */
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b trapexit
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