718cf2ccb9
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162 lines
6.2 KiB
C
162 lines
6.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: mk48txxreg.h,v 1.10 2008/04/28 20:23:50 martin Exp $
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*
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* $FreeBSD$
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*/
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/*
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* Mostek MK48Txx clocks.
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*
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* The MK48T02 has 2KB of non-volatile memory. The time-of-day clock
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* registers start at offset 0x7f8.
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*
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* The MK48T08 and MK48T18 have 8KB of non-volatile memory
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*
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* The MK48T59 also has 8KB of non-volatile memory but in addition it
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* has a battery low detection bit and a power supply wakeup alarm for
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* power management. It's at offset 0x1ff0 in the NVRAM.
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*/
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/*
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* Mostek MK48TXX register definitions
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*/
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/*
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* The first bank of eight registers at offset (nvramsz - 16) is
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* available only on recenter (which?) MK48Txx models.
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*/
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#define MK48TXX_FLAGS 0 /* flags register */
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#define MK48TXX_UNUSED 1 /* unused */
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#define MK48TXX_ASEC 2 /* alarm seconds (0..59; BCD) */
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#define MK48TXX_AMIN 3 /* alarm minutes (0..59; BCD) */
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#define MK48TXX_AHOUR 4 /* alarm hours (0..23; BCD) */
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#define MK48TXX_ADAY 5 /* alarm day in month (1..31; BCD) */
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#define MK48TXX_INTR 6 /* interrupts register */
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#define MK48TXX_WDOG 7 /* watchdog register */
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#define MK48TXX_ICSR 8 /* control register */
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#define MK48TXX_ISEC 9 /* seconds (0..59; BCD) */
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#define MK48TXX_IMIN 10 /* minutes (0..59; BCD) */
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#define MK48TXX_IHOUR 11 /* hours (0..23; BCD) */
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#define MK48TXX_IWDAY 12 /* weekday (1..7) */
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#define MK48TXX_IDAY 13 /* day in month (1..31; BCD) */
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#define MK48TXX_IMON 14 /* month (1..12; BCD) */
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#define MK48TXX_IYEAR 15 /* year (0..99; BCD) */
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/*
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* Note that some of the bits below that are not in the first eight
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* registers are also only available on models with an extended
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* register set.
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*/
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/* Bits in the flags register (extended only) */
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#define MK48TXX_FLAGS_BL 0x10 /* battery low (read only) */
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#define MK48TXX_FLAGS_AF 0x40 /* alarm flag (read only) */
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#define MK48TXX_FLAGS_WDF 0x80 /* watchdog flag (read only) */
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/* Bits in the alarm seconds register (extended only) */
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#define MK48TXX_ASEC_MASK 0x7f /* mask for alarm seconds */
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#define MK48TXX_ASEC_RPT1 0x80 /* alarm repeat mode bit 1 */
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/* Bits in the alarm minutes register (extended only) */
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#define MK48TXX_AMIN_MASK 0x7f /* mask for alarm minutes */
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#define MK48TXX_AMIN_RPT2 0x80 /* alarm repeat mode bit 2 */
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/* Bits in the alarm hours register (extended only) */
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#define MK48TXX_AHOUR_MASK 0x3f /* mask for alarm hours */
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#define MK48TXX_AHOUR_RPT3 0x80 /* alarm repeat mode bit 3 */
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/* Bits in the alarm day in month register (extended only) */
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#define MK48TXX_ADAY_MASK 0x3f /* mask for alarm day in month */
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#define MK48TXX_ADAY_RPT4 0x80 /* alarm repeat mode bit 4 */
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/* Bits in the interrupts register (extended only) */
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#define MK48TXX_INTR_ABE 0x20 /* alarm in battery back-up mode */
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#define MK48TXX_INTR_AFE 0x80 /* alarm flag enable */
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/* Bits in the watchdog register (extended only) */
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#define MK48TXX_WDOG_RB_1_16 0x00 /* watchdog resolution 1/16 second */
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#define MK48TXX_WDOG_RB_1_4 0x01 /* watchdog resolution 1/4 second */
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#define MK48TXX_WDOG_RB_1 0x02 /* watchdog resolution 1 second */
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#define MK48TXX_WDOG_RB_4 0x03 /* watchdog resolution 4 seconds */
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#define MK48TXX_WDOG_BMB_MASK 0x7c /* mask for watchdog multiplier */
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#define MK48TXX_WDOG_BMB_SHIFT 2 /* shift for watchdog multiplier */
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#define MK48TXX_WDOG_WDS 0x80 /* watchdog steering bit */
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/* Bits in the control register */
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#define MK48TXX_CSR_CALIB_MASK 0x1f /* mask for calibration step width */
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#define MK48TXX_CSR_SIGN 0x20 /* sign of above calibration witdh */
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#define MK48TXX_CSR_READ 0x40 /* want to read (freeze clock) */
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#define MK48TXX_CSR_WRITE 0x80 /* want to write */
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/* Bits in the seconds register */
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#define MK48TXX_SEC_MASK 0x7f /* mask for seconds */
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#define MK48TXX_SEC_ST 0x80 /* stop oscillator */
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/* Bits in the minutes register */
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#define MK48TXX_MIN_MASK 0x7f /* mask for minutes */
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/* Bits in the hours register */
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#define MK48TXX_HOUR_MASK 0x3f /* mask for hours */
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/* Bits in the century/weekday register */
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#define MK48TXX_WDAY_MASK 0x07 /* mask for weekday */
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#define MK48TXX_WDAY_CB 0x10 /* century bit (extended only) */
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#define MK48TXX_WDAY_CB_SHIFT 4 /* shift for century bit */
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#define MK48TXX_WDAY_CEB 0x20 /* century enable bit (extended only) */
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#define MK48TXX_WDAY_FT 0x40 /* frequency test */
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/* Bits in the day in month register */
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#define MK48TXX_DAY_MASK 0x3f /* mask for day in month */
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/* Bits in the month register */
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#define MK48TXX_MON_MASK 0x1f /* mask for month */
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/* Bits in the year register */
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#define MK48TXX_YEAR_MASK 0xff /* mask for year */
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/* Model specific NVRAM sizes and clock offsets */
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#define MK48T02_CLKSZ 2048
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#define MK48T02_CLKOFF 0x7f0
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#define MK48T08_CLKSZ 8192
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#define MK48T08_CLKOFF 0x1ff0
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#define MK48T18_CLKSZ 8192
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#define MK48T18_CLKOFF 0x1ff0
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#define MK48T37_CLKSZ 32768
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#define MK48T37_CLKOFF 0x1ff0
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#define MK48T59_CLKSZ 8192
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#define MK48T59_CLKOFF 0x1ff0
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