219d14fe5f
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
123 lines
3.3 KiB
C
123 lines
3.3 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* General Purpose IO interface.
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*
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* <hr>$Revision: 41586 $<hr>
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*/
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#ifndef __CVMX_GPIO_H__
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#define __CVMX_GPIO_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* CSR typedefs have been moved to cvmx-csr-*.h */
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/**
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* Clear the interrupt rising edge detector for the supplied
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* pins in the mask. Chips which have more than 16 GPIO pins
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* can't use them for interrupts.
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*
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* @param clear_mask Mask of pins to clear
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*/
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static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
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{
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cvmx_gpio_int_clr_t gpio_int_clr;
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gpio_int_clr.u64 = 0;
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gpio_int_clr.s.type = clear_mask;
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cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
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}
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/**
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* GPIO Read Data
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*
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* @return Status of the GPIO pins
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*/
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static inline uint32_t cvmx_gpio_read(void)
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{
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cvmx_gpio_rx_dat_t gpio_rx_dat;
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gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT);
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return gpio_rx_dat.s.dat;
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}
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/**
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* GPIO Clear pin
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*
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* @param clear_mask Bit mask to indicate which bits to drive to '0'.
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*/
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static inline void cvmx_gpio_clear(uint32_t clear_mask)
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{
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cvmx_gpio_tx_clr_t gpio_tx_clr;
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gpio_tx_clr.u64 = 0;
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gpio_tx_clr.s.clr = clear_mask;
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cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64);
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}
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/**
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* GPIO Set pin
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*
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* @param set_mask Bit mask to indicate which bits to drive to '1'.
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*/
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static inline void cvmx_gpio_set(uint32_t set_mask)
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{
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cvmx_gpio_tx_set_t gpio_tx_set;
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gpio_tx_set.u64 = 0;
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gpio_tx_set.s.set = set_mask;
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cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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