4ad6106939
* Support for sam9 "EMAC" controller.
* Support for rmii interface to phy.
at91.c & at91sam9.c:
* Eliminate separate at91sam9.c file.
* Add new devices to at91sam9_devs table.
at91_machdep.c & at at91sam9_machdep.c:
* Automatic chip type determination.
* Remove compile time chip dependencies.
* Eliminate separate at91sam9_machdep.c file.
at91_pmc.c:
* Corrected support for all of the sam926? and sam9g20 chips.
* Remove compile time chip dependencies.
My apologies to Greg for taking so long to take care of it.
331 lines
9.9 KiB
C
331 lines
9.9 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91_aicreg.h>
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#include <arm/at91/at91_pmcreg.h>
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#include <arm/at91/at91_pmcvar.h>
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struct at91rm92_softc {
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device_t dev;
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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bus_space_handle_t sc_sys_sh;
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bus_space_handle_t sc_aic_sh;
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bus_space_handle_t sc_dbg_sh;
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bus_space_handle_t sc_matrix_sh;
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};
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/*
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* Standard priority levels for the system. 0 is lowest and 7 is highest.
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* These values are the ones Atmel uses for its Linux port, which differ
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* a little form the ones that are in the standard distribution. Also,
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* the ones marked with 'TWEEK' are different based on experience.
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*/
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static const int at91_irq_prio[32] =
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{
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface */
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2, /* USB Device Port */
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4, /* Two-Wire Interface */ /* TWEEK */
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5, /* Serial Peripheral Interface */
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4, /* Serial Synchronous Controller 0 */
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6, /* Serial Synchronous Controller 1 */ /* TWEEK */
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4, /* Serial Synchronous Controller 2 */
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0, /* Timer Counter 0 */
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6, /* Timer Counter 1 */ /* TWEEK */
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0, /* Timer Counter 2 */
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0, /* Timer Counter 3 */
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0, /* Timer Counter 4 */
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0, /* Timer Counter 5 */
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2, /* USB Host port */
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3, /* Ethernet MAC */
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0, /* Advanced Interrupt Controller (IRQ0) */
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0, /* Advanced Interrupt Controller (IRQ1) */
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0, /* Advanced Interrupt Controller (IRQ2) */
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0, /* Advanced Interrupt Controller (IRQ3) */
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0, /* Advanced Interrupt Controller (IRQ4) */
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0, /* Advanced Interrupt Controller (IRQ5) */
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0 /* Advanced Interrupt Controller (IRQ6) */
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};
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#define DEVICE(_name, _id, _unit) \
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{ \
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_name, _unit, \
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AT91RM92_ ## _id ##_BASE, \
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AT91RM92_ ## _id ## _SIZE, \
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AT91RM92_IRQ_ ## _id \
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}
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static const struct cpu_devs at91_devs[] =
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{
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DEVICE("at91_pmc", PMC, 0),
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DEVICE("at91_st", ST, 0),
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DEVICE("at91_pio", PIOA, 0),
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DEVICE("at91_pio", PIOB, 1),
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DEVICE("at91_pio", PIOC, 2),
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DEVICE("at91_pio", PIOD, 3),
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DEVICE("at91_rtc", RTC, 0),
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DEVICE("at91_mci", MCI, 0),
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DEVICE("at91_twi", TWI, 0),
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DEVICE("at91_udp", UDP, 0),
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DEVICE("ate", EMAC, 0),
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DEVICE("at91_ssc", SSC0, 0),
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DEVICE("at91_ssc", SSC1, 1),
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DEVICE("at91_ssc", SSC2, 2),
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DEVICE("spi", SPI, 0),
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#ifndef SKYEYE_WORKAROUNDS
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DEVICE("uart", DBGU, 0),
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DEVICE("uart", USART0, 1),
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DEVICE("uart", USART1, 2),
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DEVICE("uart", USART2, 3),
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DEVICE("uart", USART3, 4),
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#else
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DEVICE("uart", USART0, 0),
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#endif
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DEVICE("at91_aic", AIC, 0),
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DEVICE("at91_mc", MC, 0),
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DEVICE("at91_tc", TC0, 0),
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DEVICE("at91_tc", TC1, 1),
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DEVICE("ohci", OHCI, 0),
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DEVICE("af91_cfata", CF, 0),
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{ 0, 0, 0, 0, 0 }
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};
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static void
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at91_add_child(device_t dev, int prio, const char *name, int unit,
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bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2)
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{
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device_t kid;
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struct at91_ivar *ivar;
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kid = device_add_child_ordered(dev, prio, name, unit);
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if (kid == NULL) {
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printf("Can't add child %s%d ordered\n", name, unit);
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return;
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}
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ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (ivar == NULL) {
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device_delete_child(dev, kid);
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printf("Can't add alloc ivar\n");
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return;
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}
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device_set_ivars(kid, ivar);
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resource_list_init(&ivar->resources);
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if (irq0 != -1) {
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bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
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if (irq0 != AT91RM92_IRQ_SYSTEM)
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at91_pmc_clock_add(device_get_nameunit(kid), irq0, 0);
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}
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if (irq1 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
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if (irq2 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
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if (addr != 0 && addr < AT91RM92_BASE)
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addr += AT91RM92_BASE;
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if (addr != 0)
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bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
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}
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static void
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at91_cpu_add_builtin_children(device_t dev)
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{
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int i;
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const struct cpu_devs *walker;
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for (i = 1, walker = at91_devs; walker->name; i++, walker++) {
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at91_add_child(dev, i, walker->name, walker->unit,
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walker->mem_base, walker->mem_len, walker->irq0,
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walker->irq1, walker->irq2);
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}
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}
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static uint32_t
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at91_pll_outb(int freq)
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{
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if (freq > 155000000)
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return (0x0000);
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else
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return (0x8000);
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}
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static void
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at91_identify(driver_t *drv, device_t parent)
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{
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if (at91_cpu_is(AT91_CPU_RM9200)) {
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at91_add_child(parent, 0, "at91rm920", 0, 0, 0, -1, 0, 0);
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at91_cpu_add_builtin_children(parent);
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}
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}
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static int
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at91_probe(device_t dev)
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{
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if (at91_cpu_is(AT91_CPU_RM9200)) {
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device_set_desc(dev, "AT91RM9200");
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return (0);
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}
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return (ENXIO);
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}
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static int
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at91_attach(device_t dev)
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{
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struct at91_pmc_clock *clk;
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struct at91rm92_softc *sc = device_get_softc(dev);
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int i;
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struct at91_softc *at91sc = device_get_softc(device_get_parent(dev));
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sc->sc_st = at91sc->sc_st;
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sc->sc_sh = at91sc->sc_sh;
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sc->dev = dev;
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE,
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AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0)
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panic("Enable to map system registers");
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_DBGU_BASE,
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AT91RM92_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
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panic("Enable to map DBGU registers");
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_AIC_BASE,
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AT91RM92_AIC_SIZE, &sc->sc_aic_sh) != 0)
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panic("Enable to map system registers");
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/* XXX Hack to tell atmelarm about the AIC */
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at91sc->sc_aic_sh = sc->sc_aic_sh;
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at91sc->sc_irq_system = AT91RM92_IRQ_SYSTEM;
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for (i = 0; i < 32; i++) {
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR +
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i * 4, i);
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/* Priority. */
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4,
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at91_irq_prio[i]);
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if (i < 8)
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR,
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1);
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}
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32);
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/* No debug. */
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0);
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/* Disable and clear all interrupts. */
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
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bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);
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/* Disable all interrupts for RTC (0xe24 == RTC_IDR) */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff);
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/* Disable all interrupts for the SDRAM controller */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff);
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/* Disable all interrupts for DBGU */
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bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
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/* Update USB device port clock info */
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clk = at91_pmc_clock_ref("udpck");
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clk->pmc_mask = PMC_SCER_UDP;
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at91_pmc_clock_deref(clk);
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/* Update USB host port clock info */
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clk = at91_pmc_clock_ref("uhpck");
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clk->pmc_mask = PMC_SCER_UHP;
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at91_pmc_clock_deref(clk);
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/* Each SOC has different PLL contraints */
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clk = at91_pmc_clock_ref("plla");
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clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */
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clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */
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clk->pll_min_out = RM9200_PLL_A_MIN_OUT_FREQ; /* 80 MHz */
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clk->pll_max_out = RM9200_PLL_A_MAX_OUT_FREQ; /* 180 MHz */
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clk->pll_mul_shift = RM9200_PLL_A_MUL_SHIFT;
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clk->pll_mul_mask = RM9200_PLL_A_MUL_MASK;
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clk->pll_div_shift = RM9200_PLL_A_DIV_SHIFT;
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clk->pll_div_mask = RM9200_PLL_A_DIV_MASK;
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clk->set_outb = at91_pll_outb;
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at91_pmc_clock_deref(clk);
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clk = at91_pmc_clock_ref("pllb");
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clk->pll_min_in = RM9200_PLL_B_MIN_IN_FREQ; /* 100 KHz */
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clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */
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clk->pll_min_out = RM9200_PLL_B_MIN_OUT_FREQ; /* 30 MHz */
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clk->pll_max_out = RM9200_PLL_B_MAX_OUT_FREQ; /* 240 MHz */
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clk->pll_mul_shift = RM9200_PLL_B_MUL_SHIFT;
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clk->pll_mul_mask = RM9200_PLL_B_MUL_MASK;
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clk->pll_div_shift = RM9200_PLL_B_DIV_SHIFT;
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clk->pll_div_mask = RM9200_PLL_B_DIV_MASK;
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clk->set_outb = at91_pll_outb;
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at91_pmc_clock_deref(clk);
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return (0);
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}
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static device_method_t at91_methods[] = {
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DEVMETHOD(device_probe, at91_probe),
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DEVMETHOD(device_attach, at91_attach),
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DEVMETHOD(device_identify, at91_identify),
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{0, 0},
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};
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static driver_t at91rm92_driver = {
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"at91rm920",
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at91_methods,
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sizeof(struct at91rm92_softc),
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};
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static devclass_t at91rm92_devclass;
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DRIVER_MODULE(at91rm920, atmelarm, at91rm92_driver, at91rm92_devclass, 0, 0);
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