28 lines
1016 B
LLVM
28 lines
1016 B
LLVM
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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; CHECK-DAG: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
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; CHECK-DAG: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
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; CHECK-DAG: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
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; CHECK-DAG: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
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; CHECK-DAG: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
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; CHECK-DAG: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
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define void @check_adde_addc(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64* %a4, i64* %a5) {
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b6:
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%v7 = zext i64 %a0 to i128
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%v8 = zext i64 %a1 to i128
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%v9 = shl i128 %v8, 64
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%v10 = or i128 %v7, %v9
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%v11 = zext i64 %a2 to i128
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%v12 = zext i64 %a3 to i128
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%v13 = shl i128 %v12, 64
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%v14 = or i128 %v11, %v13
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%v15 = add i128 %v10, %v14
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%v16 = lshr i128 %v15, 64
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%v17 = trunc i128 %v15 to i64
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%v18 = trunc i128 %v16 to i64
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store i64 %v17, i64* %a4
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store i64 %v18, i64* %a5
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ret void
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}
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