04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
254 lines
10 KiB
C
254 lines
10 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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* Typedefs and defines for working with Octeon physical addresses.
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*
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* <hr>$Revision: 38306 $<hr>
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*/
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#ifndef __CVMX_ADDRESS_H__
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#define __CVMX_ADDRESS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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CVMX_MIPS_SPACE_XKSEG = 3LL,
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CVMX_MIPS_SPACE_XKPHYS = 2LL,
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CVMX_MIPS_SPACE_XSSEG = 1LL,
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CVMX_MIPS_SPACE_XUSEG = 0LL
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} cvmx_mips_space_t;
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typedef enum {
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CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
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CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
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CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
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CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
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} cvmx_mips_xkseg_space_t;
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/* decodes <14:13> of a kseg3 window address */
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typedef enum {
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CVMX_ADD_WIN_SCR = 0L,
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CVMX_ADD_WIN_DMA = 1L, /* see cvmx_add_win_dma_dec_t for further decode */
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CVMX_ADD_WIN_UNUSED = 2L,
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CVMX_ADD_WIN_UNUSED2 = 3L
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} cvmx_add_win_dec_t;
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/* decode within DMA space */
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typedef enum {
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CVMX_ADD_WIN_DMA_ADD = 0L, /* add store data to the write buffer entry, allocating it if necessary */
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CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* send out the write buffer entry to DRAM */
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/* store data must be normal DRAM memory space address in this case */
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CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* send out the write buffer entry as an IOBDMA command */
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/* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
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CVMX_ADD_WIN_DMA_SENDIO = 3L, /* send out the write buffer entry as an IO write */
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/* store data must be normal IO space address in this case */
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CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* send out a single-tick command on the NCB bus */
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/* no write buffer data needed/used */
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} cvmx_add_win_dma_dec_t;
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/**
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* Physical Address Decode
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*
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* Octeon-I HW never interprets this X (<39:36> reserved
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* for future expansion), software should set to 0.
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*
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* - 0x0 XXX0 0000 0000 to DRAM Cached
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* - 0x0 XXX0 0FFF FFFF
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*
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* - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
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* - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
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*
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* - 0x0 XXX0 2000 0000 to DRAM Cached
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* - 0x0 XXXF FFFF FFFF
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*
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* - 0x1 00X0 0000 0000 to Boot Bus Uncached
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* - 0x1 00XF FFFF FFFF
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*
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* - 0x1 01X0 0000 0000 to Other NCB Uncached
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* - 0x1 FFXF FFFF FFFF devices
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*
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* Decode of all Octeon addresses
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*/
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typedef union {
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uint64_t u64;
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struct {
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cvmx_mips_space_t R : 2;
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uint64_t offset :62;
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} sva; /* mapped or unmapped virtual address */
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struct {
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uint64_t zeroes :33;
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uint64_t offset :31;
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} suseg; /* mapped USEG virtual addresses (typically) */
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struct {
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uint64_t ones :33;
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cvmx_mips_xkseg_space_t sp : 2;
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uint64_t offset :29;
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} sxkseg; /* mapped or unmapped virtual address */
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struct {
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cvmx_mips_space_t R : 2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
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uint64_t cca : 3; /* ignored by octeon */
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uint64_t mbz :10;
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uint64_t pa :49; /* physical address */
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} sxkphys; /* physical address accessed through xkphys unmapped virtual address */
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struct {
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uint64_t mbz :15;
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uint64_t is_io : 1; /* if set, the address is uncached and resides on MCB bus */
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uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */
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uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
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uint64_t offset :36;
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} sphys; /* physical address */
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struct {
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uint64_t zeroes :24; /* techically, <47:40> are dont-cares */
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uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
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uint64_t offset :36;
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} smem; /* physical mem address */
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struct {
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uint64_t mem_region :2;
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uint64_t mbz :13;
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uint64_t is_io : 1; /* 1 in this case */
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uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */
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uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
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uint64_t offset :36;
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} sio; /* physical IO address */
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struct {
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uint64_t ones : 49;
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cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_SCR (0) in this case */
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uint64_t addr : 13;
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} sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */
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/* there should only be stores to IOBDMA space, no loads */
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struct {
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uint64_t ones : 49;
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cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_DMA (1) in this case */
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uint64_t unused2: 3;
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cvmx_add_win_dma_dec_t type : 3;
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uint64_t addr : 7;
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} sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */
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struct {
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uint64_t didspace : 24;
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uint64_t unused : 40;
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} sfilldidspace;
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} cvmx_addr_t;
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/* These macros for used by 32 bit applications */
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#define CVMX_MIPS32_SPACE_KSEG0 1l
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#define CVMX_ADD_SEG32(segment, add) (((int32_t)segment << 31) | (int32_t)(add))
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/* Currently all IOs are performed using XKPHYS addressing. Linux uses the
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CvmMemCtl register to enable XKPHYS addressing to IO space from user mode.
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Future OSes may need to change the upper bits of IO addresses. The
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following define controls the upper two bits for all IO addresses generated
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by the simple executive library */
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#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
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/* These macros simplify the process of creating common IO addresses */
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#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
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#ifndef CVMX_ADD_IO_SEG
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#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
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#endif
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#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
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#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
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#define CVMX_FULL_DID(did,subdid) (((did) << 3) | (subdid))
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/* from include/ncb_rsl_id.v */
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#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
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#define CVMX_OCT_DID_GMX0 1ULL
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#define CVMX_OCT_DID_GMX1 2ULL
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#define CVMX_OCT_DID_PCI 3ULL
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#define CVMX_OCT_DID_KEY 4ULL
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#define CVMX_OCT_DID_FPA 5ULL
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#define CVMX_OCT_DID_DFA 6ULL
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#define CVMX_OCT_DID_ZIP 7ULL
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#define CVMX_OCT_DID_RNG 8ULL
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#define CVMX_OCT_DID_IPD 9ULL
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#define CVMX_OCT_DID_PKT 10ULL
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#define CVMX_OCT_DID_TIM 11ULL
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#define CVMX_OCT_DID_TAG 12ULL
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/* the rest are not on the IO bus */
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#define CVMX_OCT_DID_L2C 16ULL
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#define CVMX_OCT_DID_LMC 17ULL
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#define CVMX_OCT_DID_SPX0 18ULL
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#define CVMX_OCT_DID_SPX1 19ULL
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#define CVMX_OCT_DID_PIP 20ULL
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#define CVMX_OCT_DID_ASX0 22ULL
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#define CVMX_OCT_DID_ASX1 23ULL
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#define CVMX_OCT_DID_IOB 30ULL
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#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT,2ULL)
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#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG,0ULL)
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#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG,1ULL)
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#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
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#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
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#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
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#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
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#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
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#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
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#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY,0ULL)
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#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI,6ULL)
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#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS,0ULL)
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#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI,0ULL)
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#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD,7ULL)
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#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA,7ULL)
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#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
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#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_ADDRESS_H__ */
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