04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
335 lines
22 KiB
C
335 lines
22 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the PCI / PCIe DMA engines. These are only avialable
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* on chips with PCI / PCIe.
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*
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* <hr>$Revision: 49448 $<hr>
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*/
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#ifndef __CVMX_DMA_ENGINES_H__
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#define __CVMX_DMA_ENGINES_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum
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{
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CVMX_DMA_ENGINE_TRANSFER_OUTBOUND = 0, /**< OUTBOUND (read from L2/DRAM, write into PCI / PCIe memory space) */
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CVMX_DMA_ENGINE_TRANSFER_INBOUND = 1, /**< INBOUND (read from PCI / PCIe memory space, write into L2/DRAM) */
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CVMX_DMA_ENGINE_TRANSFER_INTERNAL = 2, /**< INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM). Only available on chips with PCIe */
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CVMX_DMA_ENGINE_TRANSFER_EXTERNAL = 3, /**< EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). Only available on chips with PCIe */
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} cvmx_dma_engine_transfer_t;
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typedef union
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{
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uint64_t u64;
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struct
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{
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uint64_t reserved_60_63 : 4; /**< Must be zero */
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uint64_t fport : 2; /**< First port. FPort indicates the physical PCIe port used for the
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PCIe memory space pointers in the FIRST POINTERS block in the
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EXTERNAL-ONLY case. Must be zero in the OUTBOUND, INBOUND and
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INTERNAL-ONLY cases. Must be zero on chips with PCI */
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uint64_t lport : 2; /**< Last port. LPort indicates the physical PCIe port used for the
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PCIe memory space pointers in the LAST POINTERS block in the
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OUTBOUND, INBOUND, and EXTERNAL-ONLY cases. Must be zero in the
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INTERNAL-ONLY case. Must be zero on chips with PCI */
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cvmx_dma_engine_transfer_t type : 2; /**< Type <20> A given PCI DMA transfer is either OUTBOUND (read from L2/DRAM,
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write into PCI / PCIe memory space), INBOUND (read from PCI / PCIe memory space, write
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into L2/DRAM), INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM), or
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EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). */
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uint64_t wqp : 1; /**< Work-queue pointer. When WQP = 1, PTR (if non-zero) is a pointer to a
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work-queue entry that is submitted by the hardware after completing the DMA;
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when WQP = 0, PTR (if non-zero) is a pointer to a byte in local memory that
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is written to 0 by the hardware after completing the DMA. */
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uint64_t c : 1; /**< C <20> Counter. 1 = use counter 1, 0 = use counter 0.
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The C bit selects between the two counters (NPEI_DMA_CNTS[DMA0,DMA1])
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that can optionally be updated after an OUTBOUND or EXTERNAL-ONLY
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transfer, and also selects between the two forced-interrupt bits
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(NPEI_INT_SUMn[DMA0_FI, DMA1_FI]) that can optionally be set after an
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OUTBOUND or EXTERNAL-ONLY transfer. C must be zero for INBOUND or
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INTERNAL-ONLY transfers. */
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uint64_t ca : 1; /**< CA <20> Counter add.
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When CA = 1, the hardware updates the selected counter after it completes the
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PCI DMA OUTBOUND or EXTERNAL-ONLY Instruction.
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- If C = 0, PCIE_DMA_CNT0 is updated
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- If C = 1, PCIE_DMA_CNT1 is updated.
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Note that this update may indirectly cause
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NPEI_INT_SUM[DCNT0,DCNT1,DTIME0,DTIME1] to become set (depending
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on the NPEI_DMA*_INT_LEVEL settings), so may cause interrupts to occur on a
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remote PCI host.
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- If NPEI_DMA_CONTROL[O_ADD1] = 1, the counter is updated by 1.
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- If NPEI_DMA_CONTROL[O_ADD1] = 0, the counter is updated by the total
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bytes in the transfer.
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When CA = 0, the hardware does not update any counters.
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For an INBOUND or INTERNAL-ONLY PCI DMA transfer, CA must never be
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set, and the hardware never adds to the counters. */
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uint64_t fi : 1; /**< FI <20> Force interrupt.
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When FI is set for an OUTBOUND or EXTERNAL-ONLY transfer, the hardware
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sets a forced interrupt bit after it completes the PCI DMA Instruction. If C = 0,
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NPEI_INT_SUMn[DMA0_FI] is set, else NPEI_INT_SUMn[DMA1_FI] is set. For
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an INBOUND or INTERNAL-ONLY PCI DMA operation, FI must never be set,
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and the hardware never generates interrupts. */
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uint64_t ii : 1; /**< II<49> Ignore the I bit (i.e. the I bit of the PCI DMA instruction local pointer).
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For OUTBOUND transfers when II = 1, ignore the I bit and the FL bit in the
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DMA HDR alone determines whether the hardware frees any/all of the local
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buffers in the FIRST POINTERS area:
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- when FL = 1, the hardware frees the local buffer when II=1.
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- when FL = 0, the hardware does not free the local buffer when II=1.
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For OUTBOUND transfers when II = 0, the I bit in the local pointer selects
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whether local buffers are freed on a pointer-by-pointer basis:
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- when (FL I) is true, the hardware frees the local buffer when II=0.
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For INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY PCI DMA transfers,
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II must never be set, and local buffers are never freed. */
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uint64_t fl : 1; /**< FL <20> Free local buffer.
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When FL = 1, for an OUTBOUND operation, it indicates that the local buffers in
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the FIRST BUFFERS area should be freed.
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If II = 1, the FL bit alone indicates whether the local buffer should be freed:
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- when FL = 1, the hardware frees the local buffer when II=1.
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- when FL = 0, the hardware does not free the local buffer when II=1.
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If II = 0, the I bit in the local pointer (refer to Section 9.5.2) determines whether
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the local buffer is freed:
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- when (FL I) is true, the hardware frees the local buffer when II=0.
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For an INBOUND, INTERNAL-ONLY, or EXTERNAL-ONLY PCI DMA transfer,
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FL must never be set, and local buffers are never freed. */
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uint64_t nlst : 4; /**< NLST <20> Number Last pointers.
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The number of pointers in the LAST POINTERS area.
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In the INBOUND, OUTBOUND, and EXTERNAL-ONLY cases, the LAST
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POINTERS area contains PCI components, and the number of 64-bit words
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required in the LAST POINTERS area is:
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- HDR.NLST + ((HDR.NLST + 3)/4) where the division removes the fraction.
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In the INTERNAL-ONLY case, the LAST POINTERS area contains local
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pointers, and the number of 64-bit words required in the LAST POINTERS area is:
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- HDR.NLST
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Note that the sum of the number of 64-bit words in the LAST POINTERS and
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FIRST POINTERS area must never exceed 31. */
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uint64_t nfst : 4; /**< NFST <20> Number First pointers.
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The number of pointers in the FIRST POINTERS area.
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In the INBOUND, OUTBOUND, and INTERNAL-ONLY cases, the FIRST
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POINTERS area contains local pointers, and the number of 64-bit words required
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in the FIRST POINTERS area is:
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- HDR.NFST
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In the EXTERNAL-ONLY case, the FIRST POINTERS area contains PCI
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components, and the number of 64-bit words required in the FIRST POINTERS
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area is:
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- HDR.NFST + ((HDR.NFST + 3)/4) where the division removes the fraction. */
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uint64_t addr : 40; /**< PTR <20> Pointer, either a work-queue-entry pointer (when WQP = 1) or a local
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memory pointer (WQP = 0).
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When WQP = 1 and PTR 0x0, the hardware inserts the work-queue entry
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indicated by PTR into a POW input queue after the PCI DMA operation is
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complete. (Section 5.4 describes the work queue entry requirements in this
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case.) When WQP = 1, PTR<2:0> must be 0x0.
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When WQP = 0 and PTR 0x0, the hardware writes the single byte in local
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memory indicated by PTR to 0x0 after the PCI DMA operation is complete.
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NPEI_DMA_CONTROL[B0_LEND] selects the endian-ness of PTR in this
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case.
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When PTR = 0x0, the hardware performs no operation after the PCI DMA
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operation is complete. */
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} s;
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} cvmx_dma_engine_header_t;
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typedef union
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{
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uint64_t u64;
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struct
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{
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uint64_t i : 1; /**< I <20> Invert free.
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This bit gives the software the ability to free buffers independently for an
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OUTBOUND PCI DMA transfer. I is not used by the hardware when II is set. I
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must not be set, and buffers are never freed, for INBOUND, INTERNAL-ONLY,
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and EXTERNAL-ONLY PCI DMA transfers. */
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uint64_t back : 4; /**< Back <20> Backup amount.
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Allows the start of a buffer that is to be freed during an OUTBOUND transfer to
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be different from the ptr value. Back specifies the amount to subtract from the
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pointer to reach the start when freeing a buffer.
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The address that is the start of the buffer being freed is:
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- Buffer start address = ((ptr >> 7) - Back) << 7.
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Back is only used by the hardware when the buffer corresponding to ptr is freed.
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Back must be 0x0, and buffers are never freed, for INBOUND, INTERNAL-ONLY,
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and EXTERNAL-ONLY PCI DMA transfers. */
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uint64_t pool : 3; /**< Pool <20> Free pool.
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Specifies which pool (of the eight hardware-managed FPA free pools) receives the
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buffer associated with ptr when freed during an OUTBOUND transfer.
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Pool is only used when the buffer corresponding to ptr is freed. Pool must be 0x0,
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and buffers are never freed, for INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY
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PCI DMA transfers. */
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uint64_t f : 1; /**< F <20> Full-block writes are allowed.
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When set, the hardware is permitted to write all the bytes in the cache blocks
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covered by ptr, ptr + Size - 1. This can improve memory system performance
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when the write misses in the L2 cache.
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F can only be set for local pointers that can be written to:
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- The local pointers in the FIRST POINTERS area that are write pointers for
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INBOUND transfers.
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- The local pointers in the LAST POINTERS area that are always write
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pointers (when present for INTERNAL-ONLY transfers).
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F must not be set for local pointers that are not written to:
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- The local pointers in the FIRST POINTERS area for OUTBOUND and
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INTERNAL-ONLY transfers. */
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uint64_t a : 1; /**< A <20> Allocate L2.
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This is a hint to the hardware that the cache blocks should be allocated in the L2
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cache (if they were not already). */
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uint64_t l : 1; /**< L <20> Little-endian.
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When L is set, the data at ptr is in little-endian format rather than big-endian. */
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uint64_t size : 13; /**< Size <20> Size in bytes of the contiguous space specified by ptr. A Size value of 0 is
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illegal. Note that the sum of the sizes in the FIRST POINTERS area must always
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exactly equal the sum of the sizes/lengths in the LAST POINTERS area:
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- In the OUTBOUND and INBOUND cases, the HDR.NFST size fields in the
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local pointers in the FIRST POINTERS area must exactly equal the lengths
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of the HDR.NLST fragments in the PCI components in the LAST POINTERS
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area.
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- In the INTERNAL-ONLY case, the HDR.NFST size fields in the local
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pointers in the FIRST POINTERS area must equal the HDR.NLST size
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fields in the local pointers in the LAST POINTERS area. */
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uint64_t reserved_36_39 : 4; /**< Must be zero */
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uint64_t addr : 36; /**< L2/DRAM byte pointer. Points to where the packet data starts.
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Ptr can be any byte alignment. Note that ptr is interpreted as a big-endian byte
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pointer when L is clear, a little-endian byte pointer when L is set. */
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} internal;
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struct
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{
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uint64_t len0 : 16; /**< Length of PCI / PCIe memory for address 0 */
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uint64_t len1 : 16; /**< Length of PCI / PCIe memory for address 1 */
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uint64_t len2 : 16; /**< Length of PCI / PCIe memory for address 2 */
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uint64_t len3 : 16; /**< Length of PCI / PCIe memory for address 3 */
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} pcie_length;
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} cvmx_dma_engine_buffer_t;
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/**
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* Initialize the DMA engines for use
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_dma_engine_initialize(void);
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/**
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* Shutdown all DMA engines. The engeines must be idle when this
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* function is called.
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_dma_engine_shutdown(void);
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/**
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* Return the number of DMA engimes supported by this chip
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*
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* @return Number of DMA engines
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*/
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int cvmx_dma_engine_get_num(void);
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/**
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* Submit a series of DMA comamnd to the DMA engines.
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*
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* @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
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* @param header Command header
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* @param num_buffers
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* The number of data pointers
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* @param buffers Comamnd data pointers
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_buffers, cvmx_dma_engine_buffer_t buffers[]);
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/**
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* Build the first and last pointers based on a DMA engine header
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* and submit them to the engine. The purpose of this function is
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* to simplify the building of DMA engine commands by automatically
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* converting a simple address and size into the apropriate internal
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* or PCI / PCIe address list. This function does not support gather lists,
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* so you will need to build your own lists in that case.
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*
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* @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
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* @param header DMA Command header. Note that the nfst and nlst fields do not
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* need to be filled in. All other fields must be set properly.
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* @param first_address
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* Address to use for the first pointers. In the case of INTERNAL,
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* INBOUND, and OUTBOUND this is an Octeon memory address. In the
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* case of EXTERNAL, this is the source PCI / PCIe address.
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* @param last_address
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* Address to use for the last pointers. In the case of EXTERNAL,
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* INBOUND, and OUTBOUND this is a PCI / PCIe address. In the
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* case of INTERNAL, this is the Octeon memory destination address.
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* @param size Size of the transfer to perform.
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header,
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uint64_t first_address, uint64_t last_address,
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int size);
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/**
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* Simplified interface to the DMA engines to emulate memcpy()
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*
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* @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
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* @param dest Pointer to the destination memory. cvmx_ptr_to_phys() will be
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* used to turn this into a physical address. It cannot be a local
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* or CVMX_SHARED block.
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* @param source Pointer to the source memory.
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* cvmx_ptr_to_phys() will be used to turn this
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* into a physical address. It cannot be a local
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* or CVMX_SHARED block.
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* @param length Number of bytes to copy
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*
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* @return Zero on success, negative on failure
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*/
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static inline int cvmx_dma_engine_memcpy(int engine, void *dest, void *source, int length)
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{
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cvmx_dma_engine_header_t header;
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header.u64 = 0;
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header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL;
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return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source),
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cvmx_ptr_to_phys(dest), length);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif // __CVMX_CMD_QUEUE_H__
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