665 lines
17 KiB
C
665 lines
17 KiB
C
/*
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* Copyright (c) 1997, 1999 Hellmuth Michaelis. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b - Siemens HSCX chip (B-channel) handling
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* --------------------------------------------
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*
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* $Id: i4b_hscx.c,v 1.2 1999/12/13 21:25:26 hm Exp $
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*
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* $FreeBSD$
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*
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* last edit-date: [Mon Dec 13 21:59:58 1999]
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*
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*---------------------------------------------------------------------------*/
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#include "isic.h"
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#if NISIC > 0
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#include <sys/param.h>
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#include <sys/ioccom.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <machine/stdarg.h>
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#include <machine/clock.h>
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#include <net/if.h>
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#include <machine/i4b_debug.h>
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#include <machine/i4b_ioctl.h>
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#include <machine/i4b_trace.h>
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#include <i4b/layer1/i4b_l1.h>
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#include <i4b/layer1/i4b_isac.h>
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#include <i4b/layer1/i4b_hscx.h>
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#include <i4b/include/i4b_l1l2.h>
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#include <i4b/include/i4b_global.h>
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#include <i4b/include/i4b_mbuf.h>
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/*---------------------------------------------------------------------------*
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* HSCX IRQ Handler
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*---------------------------------------------------------------------------*/
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void
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isic_hscx_irq(register struct l1_softc *sc, u_char ista, int h_chan, u_char ex_irq)
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{
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register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
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u_char exir = 0;
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int activity = -1;
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u_char cmd = 0;
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DBGL1(L1_H_IRQ, "isic_hscx_irq", ("%#x\n", ista));
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if(ex_irq)
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{
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/* get channel extended irq reg */
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exir = HSCX_READ(h_chan, H_EXIR);
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if(exir & HSCX_EXIR_RFO)
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{
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chan->stat_RFO++;
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("ex_irq: receive data overflow\n"));
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}
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if((exir & HSCX_EXIR_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
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{
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chan->stat_XDU++;
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("ex_irq: xmit data underrun\n"));
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isic_hscx_cmd(sc, h_chan, HSCX_CMDR_XRES);
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if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
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{
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i4b_Bfreembuf(chan->out_mbuf_head);
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chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
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}
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}
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}
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/* rx message end, end of frame */
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if(ista & HSCX_ISTA_RME)
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{
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register int fifo_data_len;
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u_char rsta;
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int error = 0;
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rsta = HSCX_READ(h_chan, H_RSTA);
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if((rsta & 0xf0) != 0xa0)
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{
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if((rsta & HSCX_RSTA_VFR) == 0)
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{
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chan->stat_VFR++;
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cmd |= (HSCX_CMDR_RHR);
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("received invalid Frame\n"));
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error++;
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}
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if(rsta & HSCX_RSTA_RDO)
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{
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chan->stat_RDO++;
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("receive data overflow\n"));
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error++;
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}
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if((rsta & HSCX_RSTA_CRC) == 0)
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{
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chan->stat_CRC++;
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cmd |= (HSCX_CMDR_RHR);
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("CRC check failed\n"));
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error++;
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}
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if(rsta & HSCX_RSTA_RAB)
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{
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chan->stat_RAB++;
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("Receive message aborted\n"));
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error++;
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}
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}
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fifo_data_len = ((HSCX_READ(h_chan, H_RBCL)) &
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((sc->sc_bfifolen)-1));
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if(fifo_data_len == 0)
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fifo_data_len = sc->sc_bfifolen;
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/* all error conditions checked, now decide and take action */
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if(error == 0)
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{
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if(chan->in_mbuf == NULL)
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{
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if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
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panic("L1 isic_hscx_irq: RME, cannot allocate mbuf!\n");
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chan->in_cbptr = chan->in_mbuf->m_data;
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chan->in_len = 0;
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}
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fifo_data_len -= 1; /* last byte in fifo is RSTA ! */
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if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
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{
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/* read data from HSCX fifo */
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HSCX_RDFIFO(h_chan, chan->in_cbptr, fifo_data_len);
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cmd |= (HSCX_CMDR_RMC);
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isic_hscx_cmd(sc, h_chan, cmd);
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cmd = 0;
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chan->in_len += fifo_data_len;
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chan->rxcount += fifo_data_len;
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/* setup mbuf data length */
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chan->in_mbuf->m_len = chan->in_len;
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chan->in_mbuf->m_pkthdr.len = chan->in_len;
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if(sc->sc_trace & TRACE_B_RX)
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{
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i4b_trace_hdr_t hdr;
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hdr.unit = sc->sc_unit;
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hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
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hdr.dir = FROM_NT;
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hdr.count = ++sc->sc_trace_bcount;
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MICROTIME(hdr.time);
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MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
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}
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(*chan->drvr_linktab->bch_rx_data_ready)(chan->drvr_linktab->unit);
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activity = ACT_RX;
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/* mark buffer ptr as unused */
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chan->in_mbuf = NULL;
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chan->in_cbptr = NULL;
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chan->in_len = 0;
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}
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else
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{
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("RAWHDLC rx buffer overflow in RME, in_len=%d, fifolen=%d\n", chan->in_len, fifo_data_len));
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chan->in_cbptr = chan->in_mbuf->m_data;
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chan->in_len = 0;
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cmd |= (HSCX_CMDR_RHR | HSCX_CMDR_RMC);
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}
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}
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else
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{
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if (chan->in_mbuf != NULL)
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{
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i4b_Bfreembuf(chan->in_mbuf);
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chan->in_mbuf = NULL;
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chan->in_cbptr = NULL;
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chan->in_len = 0;
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}
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cmd |= (HSCX_CMDR_RMC);
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}
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}
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/* rx fifo full */
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if(ista & HSCX_ISTA_RPF)
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{
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if(chan->in_mbuf == NULL)
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{
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if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
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panic("L1 isic_hscx_irq: RPF, cannot allocate mbuf!\n");
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chan->in_cbptr = chan->in_mbuf->m_data;
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chan->in_len = 0;
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}
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chan->rxcount += sc->sc_bfifolen;
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if((chan->in_len + sc->sc_bfifolen) <= BCH_MAX_DATALEN)
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{
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/* read data from HSCX fifo */
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HSCX_RDFIFO(h_chan, chan->in_cbptr, sc->sc_bfifolen);
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chan->in_cbptr += sc->sc_bfifolen;
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chan->in_len += sc->sc_bfifolen;
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}
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else
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{
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if(chan->bprot == BPROT_NONE)
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{
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/* setup mbuf data length */
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chan->in_mbuf->m_len = chan->in_len;
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chan->in_mbuf->m_pkthdr.len = chan->in_len;
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if(sc->sc_trace & TRACE_B_RX)
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{
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i4b_trace_hdr_t hdr;
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hdr.unit = sc->sc_unit;
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hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
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hdr.dir = FROM_NT;
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hdr.count = ++sc->sc_trace_bcount;
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MICROTIME(hdr.time);
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MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
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}
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/* silence detection */
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if(!(isic_hscx_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
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activity = ACT_RX;
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if(!(IF_QFULL(&chan->rx_queue)))
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{
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IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
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}
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else
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{
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i4b_Bfreembuf(chan->in_mbuf);
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}
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/* signal upper driver that data is available */
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(*chan->drvr_linktab->bch_rx_data_ready)(chan->drvr_linktab->unit);
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/* alloc new buffer */
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if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
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panic("L1 isic_hscx_irq: RPF, cannot allocate new mbuf!\n");
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/* setup new data ptr */
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chan->in_cbptr = chan->in_mbuf->m_data;
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/* read data from HSCX fifo */
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HSCX_RDFIFO(h_chan, chan->in_cbptr, sc->sc_bfifolen);
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chan->in_cbptr += sc->sc_bfifolen;
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chan->in_len = sc->sc_bfifolen;
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chan->rxcount += sc->sc_bfifolen;
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}
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else
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{
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DBGL1(L1_H_XFRERR, "isic_hscx_irq", ("RAWHDLC rx buffer overflow in RPF, in_len=%d\n", chan->in_len));
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chan->in_cbptr = chan->in_mbuf->m_data;
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chan->in_len = 0;
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cmd |= (HSCX_CMDR_RHR);
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}
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}
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/* command to release fifo space */
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cmd |= HSCX_CMDR_RMC;
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}
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/* transmit fifo empty, new data can be written to fifo */
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if(ista & HSCX_ISTA_XPR)
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{
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/*
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* for a description what is going on here, please have
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* a look at isic_bchannel_start() in i4b_bchan.c !
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*/
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int activity = -1;
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int len;
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int nextlen;
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DBGL1(L1_H_IRQ, "isic_hscx_irq", ("unit %d, chan %d - XPR, Tx Fifo Empty!\n", sc->sc_unit, h_chan));
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if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
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{
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IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
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if(chan->out_mbuf_head == NULL)
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{
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chan->state &= ~HSCX_TX_ACTIVE;
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(*chan->drvr_linktab->bch_tx_queue_empty)(chan->drvr_linktab->unit);
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}
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else
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{
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chan->state |= HSCX_TX_ACTIVE;
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chan->out_mbuf_cur = chan->out_mbuf_head;
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chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
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chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
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if(sc->sc_trace & TRACE_B_TX)
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{
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i4b_trace_hdr_t hdr;
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hdr.unit = sc->sc_unit;
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hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
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hdr.dir = FROM_TE;
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hdr.count = ++sc->sc_trace_bcount;
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MICROTIME(hdr.time);
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MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
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}
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if(chan->bprot == BPROT_NONE)
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{
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if(!(isic_hscx_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
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activity = ACT_TX;
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}
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else
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{
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activity = ACT_TX;
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}
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}
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}
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len = 0;
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while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
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{
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nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
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#ifdef NOTDEF
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printf("i:mh=%x, mc=%x, mcp=%x, mcl=%d l=%d nl=%d # ",
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chan->out_mbuf_head,
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chan->out_mbuf_cur,
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chan->out_mbuf_cur_ptr,
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chan->out_mbuf_cur_len,
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len,
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next_len);
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#endif
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isic_hscx_waitxfw(sc, h_chan); /* necessary !!! */
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HSCX_WRFIFO(h_chan, chan->out_mbuf_cur_ptr, nextlen);
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cmd |= HSCX_CMDR_XTF;
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len += nextlen;
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chan->txcount += nextlen;
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chan->out_mbuf_cur_ptr += nextlen;
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chan->out_mbuf_cur_len -= nextlen;
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if(chan->out_mbuf_cur_len == 0)
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{
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if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
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{
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chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
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chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
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if(sc->sc_trace & TRACE_B_TX)
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{
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i4b_trace_hdr_t hdr;
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hdr.unit = sc->sc_unit;
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hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
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hdr.dir = FROM_TE;
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hdr.count = ++sc->sc_trace_bcount;
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MICROTIME(hdr.time);
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MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
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}
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}
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else
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{
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if (chan->bprot != BPROT_NONE)
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cmd |= HSCX_CMDR_XME;
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i4b_Bfreembuf(chan->out_mbuf_head);
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chan->out_mbuf_head = NULL;
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}
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}
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}
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}
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if(cmd) /* is there a command for the HSCX ? */
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{
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isic_hscx_cmd(sc, h_chan, cmd); /* yes, to HSCX */
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}
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/* call timeout handling routine */
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if(activity == ACT_RX || activity == ACT_TX)
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(*chan->drvr_linktab->bch_activity)(chan->drvr_linktab->unit, activity);
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}
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/*---------------------------------------------------------------------------*
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* HSCX initialization
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*
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* for telephony: extended transparent mode 1
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* for raw hdlc: transparent mode 0
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*---------------------------------------------------------------------------*/
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void
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isic_hscx_init(struct l1_softc *sc, int h_chan, int activate)
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{
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l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
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HSCX_WRITE(h_chan, H_MASK, 0xff); /* mask irq's */
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if(sc->sc_ipac)
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{
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/* CCR1: Power Up, Clock Mode 5 */
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HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
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HSCX_CCR1_CM1); /* IPAC clock mode 5 */
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}
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else
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{
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/* CCR1: Power Up, Clock Mode 5 */
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HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
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HSCX_CCR1_CM2 | /* HSCX clock mode 5 */
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HSCX_CCR1_CM0);
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}
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/* XAD1: Transmit Address Byte 1 */
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HSCX_WRITE(h_chan, H_XAD1, 0xff);
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/* XAD2: Transmit Address Byte 2 */
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HSCX_WRITE(h_chan, H_XAD2, 0xff);
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/* RAH2: Receive Address Byte High Reg. 2 */
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HSCX_WRITE(h_chan, H_RAH2, 0xff);
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/* XBCH: reset Transmit Byte Count High */
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HSCX_WRITE(h_chan, H_XBCH, 0x00);
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/* RLCR: reset Receive Length Check Register */
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HSCX_WRITE(h_chan, H_RLCR, 0x00);
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/* CCR2: set tx/rx clock shift bit 0 */
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|
/* disable CTS irq, disable RIE irq*/
|
|
HSCX_WRITE(h_chan, H_CCR2, HSCX_CCR2_XCS0|HSCX_CCR2_RCS0);
|
|
|
|
/* XCCR: tx bit count per time slot */
|
|
HSCX_WRITE(h_chan, H_XCCR, 0x07);
|
|
|
|
/* RCCR: rx bit count per time slot */
|
|
HSCX_WRITE(h_chan, H_RCCR, 0x07);
|
|
|
|
if(sc->sc_bustyp == BUS_TYPE_IOM2)
|
|
{
|
|
switch(h_chan)
|
|
{
|
|
case HSCX_CH_A: /* Prepare HSCX channel A */
|
|
/* TSAX: tx clock shift bits 1 & 2 */
|
|
/* tx time slot number */
|
|
HSCX_WRITE(h_chan, H_TSAX, 0x2f);
|
|
|
|
/* TSAR: rx clock shift bits 1 & 2 */
|
|
/* rx time slot number */
|
|
HSCX_WRITE(h_chan, H_TSAR, 0x2f);
|
|
break;
|
|
|
|
case HSCX_CH_B: /* Prepare HSCX channel B */
|
|
/* TSAX: tx clock shift bits 1 & 2 */
|
|
/* tx time slot number */
|
|
HSCX_WRITE(h_chan, H_TSAX, 0x03);
|
|
|
|
/* TSAR: rx clock shift bits 1 & 2 */
|
|
/* rx time slot number */
|
|
HSCX_WRITE(h_chan, H_TSAR, 0x03);
|
|
break;
|
|
}
|
|
}
|
|
else /* IOM 1 setup */
|
|
{
|
|
/* TSAX: tx clock shift bits 1 & 2 */
|
|
/* tx time slot number */
|
|
HSCX_WRITE(h_chan, H_TSAX, 0x07);
|
|
|
|
/* TSAR: rx clock shift bits 1 & 2 */
|
|
/* rx time slot number */
|
|
HSCX_WRITE(h_chan, H_TSAR, 0x07);
|
|
}
|
|
|
|
if(activate)
|
|
{
|
|
if(chan->bprot == BPROT_RHDLC)
|
|
{
|
|
/* HDLC Frames, transparent mode 0 */
|
|
HSCX_WRITE(h_chan, H_MODE,
|
|
HSCX_MODE_MDS1|HSCX_MODE_RAC|HSCX_MODE_RTS);
|
|
}
|
|
else
|
|
{
|
|
/* Raw Telephony, extended transparent mode 1 */
|
|
HSCX_WRITE(h_chan, H_MODE,
|
|
HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
|
|
}
|
|
|
|
isic_hscx_cmd(sc, h_chan, HSCX_CMDR_RHR|HSCX_CMDR_XRES);
|
|
}
|
|
else
|
|
{
|
|
/* TSAX: tx time slot */
|
|
HSCX_WRITE(h_chan, H_TSAX, 0xff);
|
|
|
|
/* TSAR: rx time slot */
|
|
HSCX_WRITE(h_chan, H_TSAR, 0xff);
|
|
|
|
/* Raw Telephony, extended transparent mode 1 */
|
|
HSCX_WRITE(h_chan, H_MODE,
|
|
HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
|
|
}
|
|
|
|
/* don't touch ICA, EXA and EXB bits, this could be HSCX_CH_B */
|
|
/* always disable RSC and TIN */
|
|
|
|
chan->hscx_mask |= HSCX_MASK_RSC | HSCX_MASK_TIN;
|
|
|
|
if(activate)
|
|
{
|
|
/* enable */
|
|
chan->hscx_mask &= ~(HSCX_MASK_RME | HSCX_MASK_RPF | HSCX_MASK_XPR);
|
|
}
|
|
else
|
|
{
|
|
/* disable */
|
|
chan->hscx_mask |= HSCX_MASK_RME | HSCX_MASK_RPF | HSCX_MASK_XPR;
|
|
}
|
|
|
|
/* handle ICA, EXA, and EXB via interrupt mask of channel b */
|
|
|
|
if (h_chan == HSCX_CH_A)
|
|
{
|
|
if (activate)
|
|
HSCX_B_IMASK &= ~(HSCX_MASK_EXA | HSCX_MASK_ICA);
|
|
else
|
|
HSCX_B_IMASK |= HSCX_MASK_EXA | HSCX_MASK_ICA;
|
|
HSCX_WRITE(HSCX_CH_A, H_MASK, HSCX_A_IMASK);
|
|
HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
|
|
}
|
|
else
|
|
{
|
|
if (activate)
|
|
HSCX_B_IMASK &= ~HSCX_MASK_EXB;
|
|
else
|
|
HSCX_B_IMASK |= HSCX_MASK_EXB;
|
|
HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
|
|
}
|
|
|
|
/* clear spurious interrupts left over */
|
|
|
|
if(h_chan == HSCX_CH_A)
|
|
{
|
|
HSCX_READ(h_chan, H_EXIR);
|
|
HSCX_READ(h_chan, H_ISTA);
|
|
}
|
|
else /* mask ICA, because it must not be cleared by reading ISTA */
|
|
{
|
|
HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK | HSCX_MASK_ICA);
|
|
HSCX_READ(h_chan, H_EXIR);
|
|
HSCX_READ(h_chan, H_ISTA);
|
|
HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* write command to HSCX command register
|
|
*---------------------------------------------------------------------------*/
|
|
void
|
|
isic_hscx_cmd(struct l1_softc *sc, int h_chan, unsigned char cmd)
|
|
{
|
|
int timeout = 20;
|
|
|
|
while(((HSCX_READ(h_chan, H_STAR)) & HSCX_STAR_CEC) && timeout)
|
|
{
|
|
DELAY(10);
|
|
timeout--;
|
|
}
|
|
|
|
if(timeout == 0)
|
|
{
|
|
DBGL1(L1_H_ERR, "isic_hscx_cmd", ("HSCX wait for CEC timeout!\n"));
|
|
}
|
|
|
|
HSCX_WRITE(h_chan, H_CMDR, cmd);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* wait for HSCX transmit FIFO write enable
|
|
*---------------------------------------------------------------------------*/
|
|
void
|
|
isic_hscx_waitxfw(struct l1_softc *sc, int h_chan)
|
|
{
|
|
#define WAITVAL 50
|
|
#define WAITTO 200
|
|
|
|
int timeout = WAITTO;
|
|
|
|
while((!(((HSCX_READ(h_chan, H_STAR)) &
|
|
(HSCX_STAR_CEC | HSCX_STAR_XFW)) == HSCX_STAR_XFW)) && timeout)
|
|
{
|
|
DELAY(WAITVAL);
|
|
timeout--;
|
|
}
|
|
|
|
if(timeout == 0)
|
|
{
|
|
DBGL1(L1_H_ERR, "isic_hscx_waitxfw", ("HSCX wait for XFW timeout!\n"));
|
|
}
|
|
else if (timeout != WAITTO)
|
|
{
|
|
DBGL1(L1_H_XFRERR, "isic_hscx_waitxfw", ("HSCX wait for XFW time: %d uS\n", (WAITTO-timeout)*50));
|
|
}
|
|
}
|
|
|
|
#endif /* NISIC > 0 */
|