1713e81b9c
providing the original driver, and thanks to IronSystems for providing hardware for testing.
211 lines
8.4 KiB
C
211 lines
8.4 KiB
C
/*
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* Copyright (c) 2003-2004 MARVELL SEMICONDUCTOR ISRAEL, LTD.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __INCmvStorageDevh
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#define __INCmvStorageDevh
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/* Definitions */
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/* ATA register on the ATA drive*/
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#define MV_EDMA_ATA_FEATURES_ADDR 0x11
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#define MV_EDMA_ATA_SECTOR_COUNT_ADDR 0x12
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#define MV_EDMA_ATA_LBA_LOW_ADDR 0x13
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#define MV_EDMA_ATA_LBA_MID_ADDR 0x14
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#define MV_EDMA_ATA_LBA_HIGH_ADDR 0x15
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#define MV_EDMA_ATA_DEVICE_ADDR 0x16
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#define MV_EDMA_ATA_COMMAND_ADDR 0x17
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#define MV_ATA_ERROR_STATUS 0x00000001 /* MV_BIT0 */
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#define MV_ATA_DATA_REQUEST_STATUS 0x00000008 /* MV_BIT3 */
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#define MV_ATA_SERVICE_STATUS 0x00000010 /* MV_BIT4 */
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#define MV_ATA_DEVICE_FAULT_STATUS 0x00000020 /* MV_BIT5 */
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#define MV_ATA_READY_STATUS 0x00000040 /* MV_BIT6 */
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#define MV_ATA_BUSY_STATUS 0x00000080 /* MV_BIT7 */
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#define MV_ATA_COMMAND_READ_SECTORS 0x20
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#define MV_ATA_COMMAND_READ_SECTORS_EXT 0x24
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#define MV_ATA_COMMAND_READ_VERIFY_SECTORS 0x40
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#define MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT 0x42
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#define MV_ATA_COMMAND_READ_BUFFER 0xE4
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#define MV_ATA_COMMAND_WRITE_BUFFER 0xE8
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#define MV_ATA_COMMAND_WRITE_SECTORS 0x30
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#define MV_ATA_COMMAND_WRITE_SECTORS_EXT 0x34
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#define MV_ATA_COMMAND_DIAGNOSTIC 0x90
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#define MV_ATA_COMMAND_SMART 0xb0
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#define MV_ATA_COMMAND_READ_MULTIPLE 0xc4
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#define MV_ATA_COMMAND_WRITE_MULTIPLE 0xc5
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#define MV_ATA_COMMAND_STANDBY_IMMEDIATE 0xe0
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#define MV_ATA_COMMAND_IDLE_IMMEDIATE 0xe1
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#define MV_ATA_COMMAND_STANDBY 0xe2
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#define MV_ATA_COMMAND_IDLE 0xe3
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#define MV_ATA_COMMAND_SLEEP 0xe6
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#define MV_ATA_COMMAND_IDENTIFY 0xec
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#define MV_ATA_COMMAND_DEVICE_CONFIG 0xb1
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#define MV_ATA_COMMAND_SET_FEATURES 0xef
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#define MV_ATA_COMMAND_WRITE_DMA 0xca
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#define MV_ATA_COMMAND_WRITE_DMA_EXT 0x35
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#define MV_ATA_COMMAND_WRITE_DMA_QUEUED 0xcc
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#define MV_ATA_COMMAND_WRITE_DMA_QUEUED_EXT 0x36
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#define MV_ATA_COMMAND_WRITE_FPDMA_QUEUED_EXT 0x61
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#define MV_ATA_COMMAND_READ_DMA 0xc8
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#define MV_ATA_COMMAND_READ_DMA_EXT 0x25
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#define MV_ATA_COMMAND_READ_DMA_QUEUED 0xc7
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#define MV_ATA_COMMAND_READ_DMA_QUEUED_EXT 0x26
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#define MV_ATA_COMMAND_READ_FPDMA_QUEUED_EXT 0x60
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#define MV_ATA_COMMAND_FLUSH_CACHE 0xe7
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#define MV_ATA_COMMAND_FLUSH_CACHE_EXT 0xea
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#define MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO 0x01
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#define MV_ATA_SET_FEATURES_ENABLE_WCACHE 0x02 /* Enable write cache */
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#define MV_ATA_SET_FEATURES_TRANSFER 0x03 /* Set transfer mode */
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#define MV_ATA_TRANSFER_UDMA_0 0x40
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#define MV_ATA_TRANSFER_UDMA_1 0x41
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#define MV_ATA_TRANSFER_UDMA_2 0x42
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#define MV_ATA_TRANSFER_UDMA_3 0x43
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#define MV_ATA_TRANSFER_UDMA_4 0x44
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#define MV_ATA_TRANSFER_UDMA_5 0x45
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#define MV_ATA_TRANSFER_UDMA_6 0x46
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#define MV_ATA_TRANSFER_UDMA_7 0x47
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#define MV_ATA_TRANSFER_PIO_SLOW 0x00
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#define MV_ATA_TRANSFER_PIO_0 0x08
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#define MV_ATA_TRANSFER_PIO_1 0x09
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#define MV_ATA_TRANSFER_PIO_2 0x0A
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#define MV_ATA_TRANSFER_PIO_3 0x0B
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#define MV_ATA_TRANSFER_PIO_4 0x0C
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/* Enable advanced power management */
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#define MV_ATA_SET_FEATURES_ENABLE_APM 0x05
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/* Disable media status notification*/
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#define MV_ATA_SET_FEATURES_DISABLE_MSN 0x31
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/* Disable read look-ahead */
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#define MV_ATA_SET_FEATURES_DISABLE_RLA 0x55
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/* Enable release interrupt */
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#define MV_ATA_SET_FEATURES_ENABLE_RI 0x5D
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/* Enable SERVICE interrupt */
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#define MV_ATA_SET_FEATURES_ENABLE_SI 0x5E
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/* Disable revert power-on defaults */
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#define MV_ATA_SET_FEATURES_DISABLE_RPOD 0x66
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/* Disable write cache */
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#define MV_ATA_SET_FEATURES_DISABLE_WCACHE 0x82
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/* Disable advanced power management*/
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#define MV_ATA_SET_FEATURES_DISABLE_APM 0x85
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/* Enable media status notification */
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#define MV_ATA_SET_FEATURES_ENABLE_MSN 0x95
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/* Enable read look-ahead */
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#define MV_ATA_SET_FEATURES_ENABLE_RLA 0xAA
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/* Enable revert power-on defaults */
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#define MV_ATA_SET_FEATURES_ENABLE_RPOD 0xCC
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/* Disable release interrupt */
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#define MV_ATA_SET_FEATURES_DISABLE_RI 0xDD
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/* Disable SERVICE interrupt */
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#define MV_ATA_SET_FEATURES_DISABLE_SI 0xDE
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/* Defines for parsing the IDENTIFY command results*/
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#define IDEN_SERIAL_NUM_OFFSET 10
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#define IDEN_SERIAL_NUM_SIZE 19-10
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#define IDEN_FIRMWARE_OFFSET 23
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#define IDEN_FIRMWARE_SIZE 26-23
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#define IDEN_MODEL_OFFSET 27
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#define IDEN_MODEL_SIZE 46-27
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#define IDEN_CAPACITY_1_OFFSET 49
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#define IDEN_VALID 53
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#define IDEN_NUM_OF_ADDRESSABLE_SECTORS 60
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#define IDEN_PIO_MODE_SPPORTED 64
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#define IDEN_QUEUE_DEPTH 75
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#define IDEN_SATA_CAPABILITIES 76
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#define IDEN_SATA_FEATURES_SUPPORTED 78
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#define IDEN_SATA_FEATURES_ENABLED 79
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#define IDEN_ATA_VERSION 80
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#define IDEN_SUPPORTED_COMMANDS1 82
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#define IDEN_SUPPORTED_COMMANDS2 83
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#define IDEN_ENABLED_COMMANDS1 85
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#define IDEN_ENABLED_COMMANDS2 86
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#define IDEN_UDMA_MODE 88
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#define IDEN_SATA_CAPABILITY 76
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/* Typedefs */
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/* Structures */
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typedef struct mvStorageDevRegisters
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{
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/* Fields set by CORE driver */
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MV_U8 errorRegister;
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MV_U16 sectorCountRegister;
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MV_U16 lbaLowRegister;
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MV_U16 lbaMidRegister;
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MV_U16 lbaHighRegister;
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MV_U8 deviceRegister;
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MV_U8 statusRegister;
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} MV_STORAGE_DEVICE_REGISTERS;
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/* Bits for HD_ERROR */
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#define NM_ERR 0x02 /* media present */
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#define ABRT_ERR 0x04 /* Command aborted */
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#define MCR_ERR 0x08 /* media change request */
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#define IDNF_ERR 0x10 /* ID field not found */
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#define MC_ERR 0x20 /* media changed */
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#define UNC_ERR 0x40 /* Uncorrect data */
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#define WP_ERR 0x40 /* write protect */
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#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
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/* Function */
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MV_BOOLEAN HPTLIBAPI mvStorageDevATAExecuteNonUDMACommand(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex,
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MV_NON_UDMA_PROTOCOL protocolType,
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MV_BOOLEAN isEXT,
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MV_U16 FAR *bufPtr, MV_U32 count,
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MV_U16 features,
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MV_U16 sectorCount,
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MV_U16 lbaLow, MV_U16 lbaMid,
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MV_U16 lbaHigh, MV_U8 device,
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MV_U8 command);
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MV_BOOLEAN HPTLIBAPI mvStorageDevATAIdentifyDevice(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvStorageDevATASetFeatures(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex, MV_U8 subCommand,
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MV_U8 subCommandSpecific1,
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MV_U8 subCommandSpecific2,
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MV_U8 subCommandSpecific3,
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MV_U8 subCommandSpecific4);
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MV_BOOLEAN HPTLIBAPI mvStorageDevATAIdleImmediate(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvStorageDevATAFlushWriteCache(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvStorageDevATASoftResetDevice(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvReadWrite(MV_SATA_CHANNEL *pSataChannel, LBA_T Lba, UCHAR Cmd, void *tmpBuffer);
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#endif
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