b8821f8415
On armv4 these are defined as synonyms right now, but it's a bit ambiguous what NOCACHE means (is buffering/write-combining also enabled or not?); this is a first step towards replacing PTE_NOCACHE with a less ambiguous name.
187 lines
5.2 KiB
C
187 lines
5.2 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/pte.h>
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#include <machine/vmparam.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include <arm/mv/mvwin.h>
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/*
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* Virtual address space layout:
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* -----------------------------
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* 0x0000_0000 - 0xbfff_ffff : user process
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*
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* 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
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* : structures, ARM stacks etc.)
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* virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
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* 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
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* 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
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* 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
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* 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
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* 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
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* 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
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* 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
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* 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
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* 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
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* 0xffff_2000 - 0xffff_ffff : unused (~55KB)
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*/
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#if 0
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int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
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/* Static device mappings. */
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const struct pmap_devmap pmap_devmap[] = {
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/*
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* Map the on-board devices VA == PA so that we can access them
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* with the MMU on or off.
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*/
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{ /* SoC integrated peripherals registers range */
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MV_BASE,
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MV_PHYS_BASE,
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MV_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCIE I/O */
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MV_PCIE_IO_BASE,
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MV_PCIE_IO_PHYS_BASE,
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MV_PCIE_IO_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCIE Memory */
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MV_PCIE_MEM_BASE,
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MV_PCIE_MEM_PHYS_BASE,
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MV_PCIE_MEM_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCI I/O */
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MV_PCI_IO_BASE,
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MV_PCI_IO_PHYS_BASE,
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MV_PCI_IO_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCI Memory */
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MV_PCI_MEM_BASE,
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MV_PCI_MEM_PHYS_BASE,
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MV_PCI_MEM_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* 7-seg LED */
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MV_DEV_CS0_BASE,
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MV_DEV_CS0_PHYS_BASE,
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MV_DEV_CS0_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ 0, 0, 0, 0, 0, }
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};
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/*
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* The pci_irq_map table consists of 3 columns:
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* - PCI slot number (less than zero means ANY).
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* - PCI IRQ pin (less than zero means ANY).
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* - PCI IRQ (less than zero marks end of table).
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*
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* IRQ number from the first matching entry is used to configure PCI device
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*/
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/* PCI IRQ Map for DB-88F5281 */
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const struct obio_pci_irq_map pci_irq_map[] = {
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{ 7, -1, GPIO2IRQ(12) },
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{ 8, -1, GPIO2IRQ(13) },
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{ 9, -1, GPIO2IRQ(13) },
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{ -1, -1, -1 }
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};
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/* PCI IRQ Map for DB-88F5182 */
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const struct obio_pci_irq_map pci_irq_map[] = {
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{ 7, -1, GPIO2IRQ(0) },
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{ 8, -1, GPIO2IRQ(1) },
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{ 9, -1, GPIO2IRQ(1) },
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{ -1, -1, -1 }
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};
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#endif
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#if 0
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/*
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* mv_gpio_config row structure:
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* <GPIO number>, <GPIO flags>, <GPIO mode>
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*
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* - GPIO pin number (less than zero marks end of table)
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* - GPIO flags:
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* MV_GPIO_BLINK
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* MV_GPIO_POLAR_LOW
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* MV_GPIO_EDGE
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* MV_GPIO_LEVEL
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* - GPIO mode:
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* 1 - Output, set to HIGH.
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* 0 - Output, set to LOW.
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* -1 - Input.
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*/
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/* GPIO Configuration for DB-88F5281 */
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const struct gpio_config mv_gpio_config[] = {
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{ 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
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{ 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
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{ -1, -1, -1 }
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};
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#if 0
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/* GPIO Configuration for DB-88F5182 */
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const struct gpio_config mv_gpio_config[] = {
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{ 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
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{ 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
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{ -1, -1, -1 }
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};
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#endif
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#endif
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