7113afc84c
This patch has the driver for 10Gigabit Ethernet controller in AMD SoC. This driver is written compatible to the Iflib framework. The existing driver is for the old version of hardware. The submitted driver here is for the recent versions of the hardware where the Ethernet controller is PCI-E based. Submitted by: Rajesh Kumar <rajesh1.kumar@amd.com> MFC after: 1 month Relnotes: yes Differential Revision: https://reviews.freebsd.org/D25793
533 lines
16 KiB
C
533 lines
16 KiB
C
/*
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* AMD 10Gb Ethernet driver
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*
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* Copyright (c) 2020 Advanced Micro Devices, Inc.
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*
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* This file is available to you under your choice of the following two
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* licenses:
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*
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* License 1: GPLv2
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*
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* This file is free software; you may copy, redistribute and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or (at
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* your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* License 2: Modified BSD
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "xgbe.h"
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#include "xgbe-common.h"
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#define XGBE_ABORT_COUNT 500
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#define XGBE_DISABLE_COUNT 1000
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#define XGBE_STD_SPEED 1
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#define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
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#define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
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#define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
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#define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
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#define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \
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XGBE_INTR_TX_EMPTY | \
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XGBE_INTR_TX_ABRT | \
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XGBE_INTR_STOP_DET)
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#define XGBE_I2C_READ BIT(8)
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#define XGBE_I2C_STOP BIT(9)
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static int
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xgbe_i2c_abort(struct xgbe_prv_data *pdata)
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{
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unsigned int wait = XGBE_ABORT_COUNT;
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/* Must be enabled to recognize the abort request */
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
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/* Issue the abort */
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
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while (wait--) {
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if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
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return (0);
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DELAY(500);
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}
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return (-EBUSY);
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}
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static int
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xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
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{
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unsigned int wait = XGBE_DISABLE_COUNT;
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unsigned int mode = enable ? 1 : 0;
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while (wait--) {
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
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if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
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return (0);
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DELAY(100);
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}
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return (-EBUSY);
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}
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static int
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xgbe_i2c_disable(struct xgbe_prv_data *pdata)
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{
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unsigned int ret;
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ret = xgbe_i2c_set_enable(pdata, false);
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if (ret) {
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/* Disable failed, try an abort */
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ret = xgbe_i2c_abort(pdata);
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if (ret) {
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axgbe_error("%s: i2c_abort %d\n", __func__, ret);
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return (ret);
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}
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/* Abort succeeded, try to disable again */
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ret = xgbe_i2c_set_enable(pdata, false);
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}
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axgbe_printf(3, "%s: final i2c_disable %d\n", __func__, ret);
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return (ret);
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}
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static int
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xgbe_i2c_enable(struct xgbe_prv_data *pdata)
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{
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return (xgbe_i2c_set_enable(pdata, true));
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}
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static void
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xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
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{
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XI2C_IOREAD(pdata, IC_CLR_INTR);
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}
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static void
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xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
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{
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XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
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}
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static void
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xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
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{
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XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
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}
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static void
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xgbe_i2c_write(struct xgbe_prv_data *pdata)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int tx_slots, cmd;
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/* Configured to never receive Rx overflows, so fill up Tx fifo */
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tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
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axgbe_printf(3, "%s: tx_slots %d tx_len %d\n", __func__, tx_slots,
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state->tx_len);
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while (tx_slots && state->tx_len) {
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if (state->op->cmd == XGBE_I2C_CMD_READ)
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cmd = XGBE_I2C_READ;
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else
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cmd = *state->tx_buf++;
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axgbe_printf(3, "%s: cmd %d tx_len %d\n", __func__, cmd,
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state->tx_len);
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if (state->tx_len == 1)
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XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
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XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
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tx_slots--;
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state->tx_len--;
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}
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/* No more Tx operations, so ignore TX_EMPTY and return */
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if (!state->tx_len)
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XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
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}
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static void
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xgbe_i2c_read(struct xgbe_prv_data *pdata)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int rx_slots;
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/* Anything to be read? */
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axgbe_printf(3, "%s: op cmd %d\n", __func__, state->op->cmd);
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if (state->op->cmd != XGBE_I2C_CMD_READ)
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return;
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rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
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axgbe_printf(3, "%s: rx_slots %d rx_len %d\n", __func__, rx_slots,
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state->rx_len);
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while (rx_slots && state->rx_len) {
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*state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
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state->rx_len--;
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rx_slots--;
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}
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}
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static void
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xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, unsigned int isr)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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if (isr & XGBE_INTR_TX_ABRT) {
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state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
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XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
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}
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if (isr & XGBE_INTR_STOP_DET)
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XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
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}
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static void
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xgbe_i2c_isr(void *data)
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{
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struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int isr;
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isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
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axgbe_printf(3, "%s: isr 0x%x\n", __func__, isr);
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if (!isr)
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goto reissue_check;
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axgbe_printf(3, "%s: I2C interrupt status=%#010x\n", __func__, isr);
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xgbe_i2c_clear_isr_interrupts(pdata, isr);
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if (isr & XGBE_INTR_TX_ABRT) {
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axgbe_printf(1, "%s: I2C TX_ABRT received (%#010x) for target "
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"%#04x\n", __func__, state->tx_abort_source,
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state->op->target);
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xgbe_i2c_disable_interrupts(pdata);
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state->ret = -EIO;
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goto out;
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}
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/* Check for data in the Rx fifo */
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xgbe_i2c_read(pdata);
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/* Fill up the Tx fifo next */
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xgbe_i2c_write(pdata);
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out:
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/* Complete on an error or STOP condition */
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axgbe_printf(3, "%s: ret %d stop %d\n", __func__, state->ret,
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XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET));
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if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
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pdata->i2c_complete = true;
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return;
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reissue_check:
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/* Reissue interrupt if status is not clear */
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if (pdata->vdata->irq_reissue_support)
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XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2);
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}
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static void
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xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
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{
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unsigned int reg;
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reg = XI2C_IOREAD(pdata, IC_CON);
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XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
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XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
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XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
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XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
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XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
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XI2C_IOWRITE(pdata, IC_CON, reg);
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}
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static void
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xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
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{
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struct xgbe_i2c *i2c = &pdata->i2c;
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unsigned int reg;
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reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
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i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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MAX_SPEED_MODE);
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i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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RX_BUFFER_DEPTH);
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i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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TX_BUFFER_DEPTH);
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axgbe_printf(3, "%s: I2C features: %s=%u, %s=%u, %s=%u\n", __func__,
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"MAX_SPEED_MODE", i2c->max_speed_mode,
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"RX_BUFFER_DEPTH", i2c->rx_fifo_size,
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"TX_BUFFER_DEPTH", i2c->tx_fifo_size);
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}
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static void
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xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
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{
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XI2C_IOWRITE(pdata, IC_TAR, addr);
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}
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static void
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xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata)
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{
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xgbe_i2c_isr(pdata);
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}
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static int
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xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned long timeout;
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int ret;
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mtx_lock(&pdata->i2c_mutex);
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axgbe_printf(3, "i2c xfer started ---->>>\n");
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ret = xgbe_i2c_disable(pdata);
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if (ret) {
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axgbe_error("failed to disable i2c master\n");
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goto out;
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}
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xgbe_i2c_set_target(pdata, op->target);
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memset(state, 0, sizeof(*state));
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state->op = op;
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state->tx_len = op->len;
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state->tx_buf = op->buf;
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state->rx_len = op->len;
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state->rx_buf = op->buf;
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xgbe_i2c_clear_all_interrupts(pdata);
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ret = xgbe_i2c_enable(pdata);
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if (ret) {
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axgbe_error("failed to enable i2c master\n");
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goto out;
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}
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/* Enabling the interrupts will cause the TX FIFO empty interrupt to
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* fire and begin to process the command via the ISR.
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*/
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xgbe_i2c_enable_interrupts(pdata);
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timeout = ticks + (20 * hz);
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while (ticks < timeout) {
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if (!pdata->i2c_complete) {
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DELAY(200);
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continue;
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}
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axgbe_printf(1, "%s: I2C OP complete\n", __func__);
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break;
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}
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if ((ticks >= timeout) && !pdata->i2c_complete) {
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axgbe_error("%s: operation timed out\n", __func__);
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ret = -ETIMEDOUT;
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goto disable;
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}
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ret = state->ret;
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axgbe_printf(3, "%s: i2c xfer ret %d abrt_source 0x%x \n", __func__,
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ret, state->tx_abort_source);
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if (ret) {
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axgbe_error("%s: i2c xfer ret %d abrt_source 0x%x \n", __func__,
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ret, state->tx_abort_source);
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if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
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ret = -ENOTCONN;
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else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
|
|
ret = -EAGAIN;
|
|
}
|
|
|
|
axgbe_printf(3, "i2c xfer finished ---->>>\n");
|
|
|
|
disable:
|
|
pdata->i2c_complete = false;
|
|
xgbe_i2c_disable_interrupts(pdata);
|
|
xgbe_i2c_disable(pdata);
|
|
|
|
out:
|
|
mtx_unlock(&pdata->i2c_mutex);
|
|
return (ret);
|
|
}
|
|
|
|
static void
|
|
xgbe_i2c_stop(struct xgbe_prv_data *pdata)
|
|
{
|
|
if (!pdata->i2c.started)
|
|
return;
|
|
|
|
axgbe_printf(3, "stopping I2C\n");
|
|
|
|
pdata->i2c.started = 0;
|
|
|
|
xgbe_i2c_disable_interrupts(pdata);
|
|
xgbe_i2c_disable(pdata);
|
|
xgbe_i2c_clear_all_interrupts(pdata);
|
|
}
|
|
|
|
static int
|
|
xgbe_i2c_start(struct xgbe_prv_data *pdata)
|
|
{
|
|
if (pdata->i2c.started)
|
|
return (0);
|
|
|
|
pdata->i2c.started = 1;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xgbe_i2c_init(struct xgbe_prv_data *pdata)
|
|
{
|
|
int ret;
|
|
|
|
/* initialize lock for i2c */
|
|
mtx_init(&pdata->i2c_mutex, "xgbe i2c mutex lock", NULL, MTX_DEF);
|
|
pdata->i2c_complete = false;
|
|
|
|
xgbe_i2c_disable_interrupts(pdata);
|
|
|
|
ret = xgbe_i2c_disable(pdata);
|
|
if (ret) {
|
|
axgbe_error("failed to disable i2c master\n");
|
|
return (ret);
|
|
}
|
|
|
|
xgbe_i2c_get_features(pdata);
|
|
|
|
xgbe_i2c_set_mode(pdata);
|
|
|
|
xgbe_i2c_clear_all_interrupts(pdata);
|
|
|
|
xgbe_dump_i2c_registers(pdata);
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
|
|
{
|
|
i2c_if->i2c_init = xgbe_i2c_init;
|
|
|
|
i2c_if->i2c_start = xgbe_i2c_start;
|
|
i2c_if->i2c_stop = xgbe_i2c_stop;
|
|
|
|
i2c_if->i2c_xfer = xgbe_i2c_xfer;
|
|
|
|
i2c_if->i2c_isr = xgbe_i2c_combined_isr;
|
|
}
|