9b63136347
This is an architecture that present a thing message passing interface to the OS. You can query as to how many ports and what kind are attached and enable them and so on. A less grand view is that this is just another way to package SCSI (SPI or FC) and FC-IP into a one-driver interface set. This driver support the following hardware: LSI FC909: Single channel, 1Gbps, Fibre Channel (FC-SCSI only) LSI FC929: Dual Channel, 1-2Gbps, Fibre Channel (FC-SCSI only) LSI 53c1020: Single Channel, Ultra4 (320M) (Untested) LSI 53c1030: Dual Channel, Ultra4 (320M) Currently it's in fair shape, but expect a lot of changes over the next few weeks as it stabilizes. Credits: The driver is mostly from some folks from Jeff Roberson's company- I've been slowly migrating it to broader support that I it came to me as. The hardware used in developing support came from: FC909: LSI-Logic, Advansys (now Connetix) FC929: LSI-Logic 53c1030: Antares Microsystems (they make a very fine board!) MFC after: 3 weeks
236 lines
8.3 KiB
C
236 lines
8.3 KiB
C
/* $FreeBSD$ */
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/*
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* LSI MPT Host Adapter FreeBSD Wrapper Definitions (CAM version)
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*
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* Copyright (c) 2000, 2001 by Greg Ansley, Adam Prewett
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*
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* Partially derived from Matty Jacobs ISP driver.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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*/
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/*
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* Additional Copyright (c) 2002 by Matthew Jacob under same license.
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*/
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#ifndef _MPT_FREEBSD_H_
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#define _MPT_FREEBSD_H_
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#include <sys/ioccom.h>
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#ifdef _KERNEL
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/bus.h>
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#include <machine/bus_memio.h>
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#include <machine/bus_pio.h>
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#include <machine/bus.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <cam/cam.h>
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#include <cam/cam_debug.h>
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#include <cam/cam_ccb.h>
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#include <cam/cam_sim.h>
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#include <cam/cam_xpt.h>
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#include <cam/cam_xpt_sim.h>
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#include <cam/cam_debug.h>
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#include <cam/scsi/scsi_all.h>
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#include <cam/scsi/scsi_message.h>
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#include "opt_ddb.h"
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#define INLINE __inline
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/* Max MPT Reply we are willing to accept (must be power of 2) */
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#define MPT_REPLY_SIZE 128
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#define MPT_MAX_REQUESTS 256 /* XXX: should be derived from GlobalCredits */
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#define MPT_REQUEST_AREA 512
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#define MPT_SENSE_SIZE 32 /* included in MPT_REQUEST_SIZE */
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#define MPT_REQ_MEM_SIZE (MPT_MAX_REQUESTS * MPT_REQUEST_AREA)
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/*
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* We cannot tell prior to getting IOC facts how big the IOC's request
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* area is. Because of this we cannot tell at compile time how many
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* simple SG elements we can fit within an IOC request prior to having
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* to put in a chain element.
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*
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* Experimentally we know that the Ultra4 parts have a 96 byte request
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* element size and the Fibre Channel units have a 144 byte request
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* element size. Therefore, if we have 512-32 (== 480) bytes of request
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* area to play with, we have room for between 3 and 5 request sized
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* regions- the first of which is the command plus a simple SG list,
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* the rest of which are chained continuation SG lists. Given that the
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* normal request we use is 48 bytes w/o the first SG element, we can
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* assume we have 480-48 == 432 bytes to have simple SG elements and/or
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* chain elements. If we assume 32 bit addressing, this works out to
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* 54 SG or chain elements. If we assume 5 chain elements, then we have
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* a maximum of 49 seperate actual SG segments.
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*/
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#define MPT_SGL_MAX 49
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#define MPT_RQSL(mpt) (mpt->request_frame_size << 2)
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#define MPT_NSGL(mpt) (MPT_RQSL(mpt) / sizeof (SGE_SIMPLE32))
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#define MPT_NSGL_FIRST(mpt) \
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(((mpt->request_frame_size << 2) - \
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sizeof (MSG_SCSI_IO_REQUEST) - \
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sizeof (SGE_IO_UNION)) / sizeof (SGE_SIMPLE32))
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/*
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* Convert a physical address returned from IOC to kvm address
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* needed to access the data.
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*/
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#define MPT_REPLY_PTOV(m, x) \
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((void *)(m->reply + ((x << 1) - (u_int32_t)(m->reply_phys))))
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#define ccb_mpt_ptr sim_priv.entries[0].ptr
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#define ccb_req_ptr sim_priv.entries[1].ptr
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enum mpt_req_state {
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REQ_FREE, REQ_IN_PROGRESS, REQ_TIMEOUT, REQ_ON_CHIP, REQ_DONE
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};
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typedef struct req_entry {
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u_int16_t index; /* Index of this entry */
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union ccb *ccb; /* Request that generated this command */
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void *req_vbuf; /* Virtual Address of Entry */
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void *sense_vbuf; /* Virtual Address of sense data */
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u_int32_t req_pbuf; /* Physical Address of Entry */
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u_int32_t sense_pbuf; /* Physical Address of sense data */
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bus_dmamap_t dmap; /* DMA map for data buffer */
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SLIST_ENTRY(req_entry) link; /* Pointer to next in list */
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enum mpt_req_state debug; /* Debuging */
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u_int32_t sequence; /* Sequence Number */
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} request_t;
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/* Structure for saving proper values for modifyable PCI configuration registers */
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struct mpt_pci_cfg {
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u_int16_t Command;
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u_int16_t LatencyTimer_LineSize;
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u_int32_t IO_BAR;
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u_int32_t Mem0_BAR[2];
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u_int32_t Mem1_BAR[2];
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u_int32_t ROM_BAR;
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u_int8_t IntLine;
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u_int32_t PMCSR;
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};
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struct mpt_softc {
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device_t dev;
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int unit;
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struct mtx lock;
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/* Operational flags, set during initialization */
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int verbose; /* print debug messages */
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struct resource *pci_irq; /* Interrupt map for chip */
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void *ih; /* Interupt handle */
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/* First Memory Region (Device MEM) */
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struct resource *pci_reg; /* Register map for chip */
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int pci_reg_id; /* Resource ID */
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bus_space_tag_t pci_st; /* Bus tag for registers */
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bus_space_handle_t pci_sh; /* Bus handle for registers */
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vm_offset_t pci_pa; /* Physical Address */
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/* Second Memory Region (Diagnostic memory window) */
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/* (only used for diagnostic purposes) */
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struct resource *pci_mem; /* Register map for chip */
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int pci_mem_id; /* Resource ID */
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bus_space_tag_t pci_mst; /* Bus tag for registers */
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bus_space_handle_t pci_msh; /* Bus handle for registers */
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/* DMA Memory for IOCTLs */
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void *ioctl_mem_va; /* Virtual Addr */
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u_int32_t ioctl_mem_pa; /* Physical Addr */
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bus_dmamap_t ioctl_mem_map; /* DMA map for buffer */
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bus_dma_tag_t ioctl_mem_tag; /* DMA tag for memory alloc */
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int open; /* only allow one open at a time */
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bus_dma_tag_t parent_dmat; /* DMA tag for parent PCI bus */
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bus_dma_tag_t reply_dmat; /* DMA tag for reply memory */
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bus_dmamap_t reply_dmap; /* DMA map for reply memory */
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char *reply; /* Virtual address of reply memory */
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u_int32_t reply_phys; /* Physical address of reply memory */
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u_int32_t
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: 29,
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disabled : 1,
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is_fc : 1,
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bus : 1; /* FC929/1030 have two busses */
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u_int32_t blk_size; /* Block size transfers to IOC */
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u_int16_t mpt_global_credits;
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u_int16_t request_frame_size;
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bus_dma_tag_t buffer_dmat; /* DMA tag for mapping data buffers */
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bus_dma_tag_t request_dmat; /* DMA tag for request memroy */
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bus_dmamap_t request_dmap; /* DMA map for request memroy */
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char *request; /* Virtual address of Request memory */
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u_int32_t request_phys; /* Physical address of Request memory */
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request_t requests[MPT_MAX_REQUESTS];
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SLIST_HEAD(req_queue, req_entry) request_free_list;
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struct cam_sim *sim;
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struct cam_path *path;
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u_int32_t sequence; /* Sequence Number */
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u_int32_t timeouts; /* timeout count */
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u_int32_t success; /* timeout successes afer timeout */
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/* Opposing port in a 929, or NULL */
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struct mpt_softc *mpt2;
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/* Saved values for the PCI configuration registers */
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struct mpt_pci_cfg pci_cfg;
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};
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static INLINE void
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mpt_write(struct mpt_softc *mpt, size_t offset, u_int32_t val)
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{
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bus_space_write_4(mpt->pci_st, mpt->pci_sh, offset, val);
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}
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static INLINE u_int32_t
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mpt_read(struct mpt_softc *mpt, int offset)
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{
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return bus_space_read_4(mpt->pci_st, mpt->pci_sh, offset);
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}
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void mpt_cam_attach(struct mpt_softc *mpt);
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void mpt_cam_detach(struct mpt_softc *mpt);
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void mpt_done(struct mpt_softc *mpt, u_int32_t reply);
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void mpt_notify(struct mpt_softc *mpt, void *vmsg);
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/* mpt_pci.c declarations */
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void mpt_set_config_regs(struct mpt_softc *mpt);
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#endif /*_KERNEL */
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#endif /* _MPT_FREEBSD_H */
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