97995404be
It is disabled by default. You need to put LOADER_FIREWIRE_SUPPORT=yes in /etc/make.conf and rebuild loader to enable it. (cd /sys/boot/i386 && make clean && make && make install) You can find a short introduction of dcons at http://wiki.freebsd.org/DebugWithDcons
163 lines
5.0 KiB
C
163 lines
5.0 KiB
C
/*
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* Copyright (c) 2007 Hidetoshi Shimokawa
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the acknowledgement as bellow:
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*
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* This product includes software developed by K. Kobayashi and H. Shimokawa
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*
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#define MAX_OHCI 5
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#define CROMSIZE 0x400
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struct fw_eui64 {
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uint32_t hi, lo;
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};
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struct fwohci_softc {
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uint32_t locator;
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uint32_t devid;
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uint32_t base_addr;
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uint32_t bus_id;
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uint32_t handle;
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int32_t state;
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struct crom_src_buf *crom_src_buf;
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struct crom_src *crom_src;
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struct crom_chunk *crom_root;
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struct fw_eui64 eui;
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int speed;
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int maxrec;
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uint32_t *config_rom;
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char config_rom_buf[CROMSIZE*2]; /* double size for alignment */
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};
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int fwohci_init(struct fwohci_softc *, int);
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void fwohci_ibr(struct fwohci_softc *);
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void fwohci_poll(struct fwohci_softc *);
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#define FWOHCI_STATE_DEAD (-1)
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#define FWOHCI_STATE_INIT 0
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#define FWOHCI_STATE_ENABLED 1
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#define FWOHCI_STATE_BUSRESET 2
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#define FWOHCI_STATE_NORMAL 3
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#define OREAD(f, o) (*(volatile uint32_t *)((f)->handle + (o)))
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#define OWRITE(f, o, v) (*(volatile uint32_t *)((f)->handle + (o)) = (v))
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#define OHCI_VERSION 0x00
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#define OHCI_ATRETRY 0x08
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#define OHCI_CROMHDR 0x18
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#define OHCI_BUS_ID 0x1c
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#define OHCI_BUS_OPT 0x20
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#define OHCI_BUSIRMC (1 << 31)
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#define OHCI_BUSCMC (1 << 30)
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#define OHCI_BUSISC (1 << 29)
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#define OHCI_BUSBMC (1 << 28)
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#define OHCI_BUSPMC (1 << 27)
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#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
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OHCI_BUSBMC | OHCI_BUSPMC
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#define OHCI_EUID_HI 0x24
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#define OHCI_EUID_LO 0x28
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#define OHCI_CROMPTR 0x34
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#define OHCI_HCCCTL 0x50
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#define OHCI_HCCCTLCLR 0x54
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#define OHCI_AREQHI 0x100
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#define OHCI_AREQHICLR 0x104
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#define OHCI_AREQLO 0x108
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#define OHCI_AREQLOCLR 0x10c
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#define OHCI_PREQHI 0x110
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#define OHCI_PREQHICLR 0x114
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#define OHCI_PREQLO 0x118
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#define OHCI_PREQLOCLR 0x11c
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#define OHCI_PREQUPPER 0x120
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#define OHCI_SID_BUF 0x64
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#define OHCI_SID_CNT 0x68
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#define OHCI_SID_ERR (1 << 31)
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#define OHCI_SID_CNT_MASK 0xffc
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#define OHCI_IT_STAT 0x90
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#define OHCI_IT_STATCLR 0x94
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#define OHCI_IT_MASK 0x98
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#define OHCI_IT_MASKCLR 0x9c
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#define OHCI_IR_STAT 0xa0
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#define OHCI_IR_STATCLR 0xa4
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#define OHCI_IR_MASK 0xa8
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#define OHCI_IR_MASKCLR 0xac
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#define OHCI_LNKCTL 0xe0
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#define OHCI_LNKCTLCLR 0xe4
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#define OHCI_PHYACCESS 0xec
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#define OHCI_CYCLETIMER 0xf0
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#define OHCI_DMACTL(off) (off)
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#define OHCI_DMACTLCLR(off) (off + 4)
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#define OHCI_DMACMD(off) (off + 0xc)
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#define OHCI_DMAMATCH(off) (off + 0x10)
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#define OHCI_ATQOFF 0x180
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#define OHCI_ATQCTL OHCI_ATQOFF
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#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
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#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
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#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
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#define OHCI_ATSOFF 0x1a0
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#define OHCI_ATSCTL OHCI_ATSOFF
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#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
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#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
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#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
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#define OHCI_ARQOFF 0x1c0
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#define OHCI_ARQCTL OHCI_ARQOFF
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#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
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#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
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#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
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#define OHCI_ARSOFF 0x1e0
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#define OHCI_ARSCTL OHCI_ARSOFF
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#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
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#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
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#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
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#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
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#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
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#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
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#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
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#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
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#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
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#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
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#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
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#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
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