720 lines
17 KiB
C
720 lines
17 KiB
C
/*-
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/ic/sab82532.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK 29491200
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/*
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* NOTE: To allow us to read the baudrate divisor from the chip, we
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* copy the value written to the write-only BGR register to an unused
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* read-write register. We use TCR for that.
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*/
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static int
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sab82532_delay(struct uart_bas *bas)
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{
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int divisor, m, n;
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uint8_t bgr, ccr2;
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bgr = uart_getreg(bas, SAB_TCR);
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ccr2 = uart_getreg(bas, SAB_CCR2);
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n = (bgr & 0x3f) + 1;
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m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
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divisor = n * (1<<m);
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/* 1/10th the time to transmit 1 character (estimate). */
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return (16000000 * divisor / bas->rclk);
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}
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static int
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sab82532_divisor(int rclk, int baudrate)
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{
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int act_baud, act_div, divisor;
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int error, m, n;
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if (baudrate == 0)
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return (0);
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divisor = (rclk / (baudrate << 3) + 1) >> 1;
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if (divisor < 2 || divisor >= 1048576)
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return (0);
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/* Find the best (N+1,M) pair. */
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for (m = 1; m < 15; m++) {
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n = divisor / (1<<m);
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if (n < 1 || n > 63)
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continue;
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act_div = n * (1<<m);
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act_baud = rclk / (act_div << 4);
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/* 10 times error in percent: */
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error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
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/* 3.0% maximum error tolerance: */
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if (error < -30 || error > 30)
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continue;
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/* Got it. */
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return ((n - 1) | (m << 6));
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}
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return (0);
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}
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static void
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sab82532_flush(struct uart_bas *bas, int what)
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{
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if (what & UART_FLUSH_TRANSMITTER) {
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while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
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;
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uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
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uart_barrier(bas);
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}
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if (what & UART_FLUSH_RECEIVER) {
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while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
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;
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uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
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uart_barrier(bas);
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}
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}
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static int
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sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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int divisor;
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uint8_t ccr2, dafo;
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if (databits >= 8)
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dafo = SAB_DAFO_CHL_CS8;
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else if (databits == 7)
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dafo = SAB_DAFO_CHL_CS7;
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else if (databits == 6)
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dafo = SAB_DAFO_CHL_CS6;
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else
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dafo = SAB_DAFO_CHL_CS5;
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if (stopbits > 1)
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dafo |= SAB_DAFO_STOP;
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switch (parity) {
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case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
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case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
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case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
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case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
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case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
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default: return (EINVAL);
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}
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/* Set baudrate. */
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if (baudrate > 0) {
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divisor = sab82532_divisor(bas->rclk, baudrate);
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if (divisor == 0)
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return (EINVAL);
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uart_setreg(bas, SAB_BGR, divisor & 0xff);
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uart_barrier(bas);
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/* Allow reading the (n-1,m) tuple from the chip. */
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uart_setreg(bas, SAB_TCR, divisor & 0xff);
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uart_barrier(bas);
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ccr2 = uart_getreg(bas, SAB_CCR2);
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ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
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ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
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uart_setreg(bas, SAB_CCR2, ccr2);
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uart_barrier(bas);
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}
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uart_setreg(bas, SAB_DAFO, dafo);
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uart_barrier(bas);
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return (0);
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}
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/*
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* Low-level UART interface.
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*/
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static int sab82532_probe(struct uart_bas *bas);
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static void sab82532_init(struct uart_bas *bas, int, int, int, int);
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static void sab82532_term(struct uart_bas *bas);
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static void sab82532_putc(struct uart_bas *bas, int);
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static int sab82532_poll(struct uart_bas *bas);
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static int sab82532_getc(struct uart_bas *bas);
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struct uart_ops uart_sab82532_ops = {
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.probe = sab82532_probe,
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.init = sab82532_init,
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.term = sab82532_term,
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.putc = sab82532_putc,
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.poll = sab82532_poll,
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.getc = sab82532_getc,
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};
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static int
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sab82532_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint8_t ccr0, pvr;
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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/*
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* Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
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* Pin 4 is magical, meaning that I don't know what it does, but
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* it too has to be set to output.
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*/
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uart_setreg(bas, SAB_PCR,
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~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
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uart_barrier(bas);
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/* Disable port interrupts. */
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uart_setreg(bas, SAB_PIM, 0xff);
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uart_barrier(bas);
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/* Interrupts are active low. */
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uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
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uart_barrier(bas);
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/* Set DTR. */
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pvr = uart_getreg(bas, SAB_PVR);
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switch (bas->chan) {
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case 1:
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pvr &= ~SAB_PVR_DTR_A;
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break;
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case 2:
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pvr &= ~SAB_PVR_DTR_B;
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break;
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}
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uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
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uart_barrier(bas);
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/* power down */
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uart_setreg(bas, SAB_CCR0, 0);
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uart_barrier(bas);
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/* set basic configuration */
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ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
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uart_setreg(bas, SAB_CCR0, ccr0);
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uart_barrier(bas);
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uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
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uart_barrier(bas);
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uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
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uart_barrier(bas);
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uart_setreg(bas, SAB_CCR3, 0);
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uart_barrier(bas);
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uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
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uart_barrier(bas);
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uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
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uart_barrier(bas);
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uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
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SAB_RFC_RFTH_32CHAR);
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uart_barrier(bas);
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sab82532_param(bas, baudrate, databits, stopbits, parity);
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/* Clear interrupts. */
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uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
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uart_setreg(bas, SAB_IMR1, 0xff);
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uart_barrier(bas);
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uart_getreg(bas, SAB_ISR0);
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uart_getreg(bas, SAB_ISR1);
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uart_barrier(bas);
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sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
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/* Power up. */
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uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
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uart_barrier(bas);
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}
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static void
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sab82532_term(struct uart_bas *bas)
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{
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uint8_t pvr;
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pvr = uart_getreg(bas, SAB_PVR);
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switch (bas->chan) {
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case 1:
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pvr |= SAB_PVR_DTR_A;
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break;
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case 2:
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pvr |= SAB_PVR_DTR_B;
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break;
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}
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uart_setreg(bas, SAB_PVR, pvr);
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uart_barrier(bas);
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}
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static void
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sab82532_putc(struct uart_bas *bas, int c)
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{
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int delay, limit;
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/* 1/10th the time to transmit 1 character (estimate). */
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delay = sab82532_delay(bas);
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limit = 20;
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while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
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DELAY(delay);
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uart_setreg(bas, SAB_TIC, c);
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limit = 20;
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while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
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DELAY(delay);
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}
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static int
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sab82532_poll(struct uart_bas *bas)
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{
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if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)
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return (sab82532_getc(bas));
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return (-1);
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}
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static int
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sab82532_getc(struct uart_bas *bas)
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{
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int c, delay;
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/* 1/10th the time to transmit 1 character (estimate). */
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delay = sab82532_delay(bas);
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while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE))
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DELAY(delay);
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while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
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;
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uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
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uart_barrier(bas);
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while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
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DELAY(delay);
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c = uart_getreg(bas, SAB_RFIFO);
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uart_barrier(bas);
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/* Blow away everything left in the FIFO... */
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while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
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;
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uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
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uart_barrier(bas);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct sab82532_softc {
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struct uart_softc base;
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};
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static int sab82532_bus_attach(struct uart_softc *);
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static int sab82532_bus_detach(struct uart_softc *);
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static int sab82532_bus_flush(struct uart_softc *, int);
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static int sab82532_bus_getsig(struct uart_softc *);
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static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int sab82532_bus_ipend(struct uart_softc *);
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static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
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static int sab82532_bus_probe(struct uart_softc *);
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static int sab82532_bus_receive(struct uart_softc *);
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static int sab82532_bus_setsig(struct uart_softc *, int);
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static int sab82532_bus_transmit(struct uart_softc *);
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static kobj_method_t sab82532_methods[] = {
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KOBJMETHOD(uart_attach, sab82532_bus_attach),
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KOBJMETHOD(uart_detach, sab82532_bus_detach),
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KOBJMETHOD(uart_flush, sab82532_bus_flush),
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KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
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KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
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KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
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KOBJMETHOD(uart_param, sab82532_bus_param),
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KOBJMETHOD(uart_probe, sab82532_bus_probe),
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KOBJMETHOD(uart_receive, sab82532_bus_receive),
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KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
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KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
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{ 0, 0 }
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};
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struct uart_class uart_sab82532_class = {
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"sab82532 class",
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sab82532_methods,
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sizeof(struct sab82532_softc),
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.uc_range = 64,
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.uc_rclk = DEFAULT_RCLK
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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sab82532_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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uint8_t imr0, imr1;
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bas = &sc->sc_bas;
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if (sc->sc_sysdev == NULL)
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sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
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sc->sc_rxfifosz = 32;
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sc->sc_txfifosz = 32;
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imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
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SAB_IMR0_RPF;
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uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
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imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
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uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
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uart_barrier(bas);
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if (sc->sc_sysdev == NULL)
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sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
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(void)sab82532_bus_getsig(sc);
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return (0);
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}
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static int
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sab82532_bus_detach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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bas = &sc->sc_bas;
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uart_setreg(bas, SAB_IMR0, 0xff);
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uart_setreg(bas, SAB_IMR1, 0xff);
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uart_barrier(bas);
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uart_getreg(bas, SAB_ISR0);
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uart_getreg(bas, SAB_ISR1);
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uart_barrier(bas);
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uart_setreg(bas, SAB_CCR0, 0);
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uart_barrier(bas);
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return (0);
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}
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static int
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sab82532_bus_flush(struct uart_softc *sc, int what)
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{
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mtx_lock_spin(&sc->sc_hwmtx);
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sab82532_flush(&sc->sc_bas, what);
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mtx_unlock_spin(&sc->sc_hwmtx);
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return (0);
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}
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static int
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sab82532_bus_getsig(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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uint32_t new, old, sig;
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uint8_t pvr, star, vstr;
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bas = &sc->sc_bas;
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do {
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old = sc->sc_hwsig;
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sig = old;
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mtx_lock_spin(&sc->sc_hwmtx);
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star = uart_getreg(bas, SAB_STAR);
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SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
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vstr = uart_getreg(bas, SAB_VSTR);
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SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
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pvr = uart_getreg(bas, SAB_PVR);
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switch (bas->chan) {
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case 1:
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pvr &= SAB_PVR_DSR_A;
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break;
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case 2:
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pvr &= SAB_PVR_DSR_B;
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break;
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}
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SIGCHG(~pvr, sig, SER_DSR, SER_DDSR);
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
new = sig & ~UART_SIGMASK_DELTA;
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
return (sig);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
struct uart_bas *bas;
|
|
uint8_t dafo, mode;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
error = 0;
|
|
mtx_lock_spin(&sc->sc_hwmtx);
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
dafo = uart_getreg(bas, SAB_DAFO);
|
|
if (data)
|
|
dafo |= SAB_DAFO_XBRK;
|
|
else
|
|
dafo &= ~SAB_DAFO_XBRK;
|
|
uart_setreg(bas, SAB_DAFO, dafo);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_IFLOW:
|
|
mode = uart_getreg(bas, SAB_MODE);
|
|
if (data) {
|
|
mode &= ~SAB_MODE_RTS;
|
|
mode |= SAB_MODE_FRTS;
|
|
} else {
|
|
mode |= SAB_MODE_RTS;
|
|
mode &= ~SAB_MODE_FRTS;
|
|
}
|
|
uart_setreg(bas, SAB_MODE, mode);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_OFLOW:
|
|
mode = uart_getreg(bas, SAB_MODE);
|
|
if (data)
|
|
mode &= ~SAB_MODE_FCTS;
|
|
else
|
|
mode |= SAB_MODE_FCTS;
|
|
uart_setreg(bas, SAB_MODE, mode);
|
|
uart_barrier(bas);
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int ipend;
|
|
uint8_t isr0, isr1;
|
|
|
|
bas = &sc->sc_bas;
|
|
mtx_lock_spin(&sc->sc_hwmtx);
|
|
isr0 = uart_getreg(bas, SAB_ISR0);
|
|
isr1 = uart_getreg(bas, SAB_ISR1);
|
|
uart_barrier(bas);
|
|
if (isr0 & SAB_ISR0_TIME) {
|
|
while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
|
|
;
|
|
uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
|
|
uart_barrier(bas);
|
|
}
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
|
|
ipend = 0;
|
|
if (isr1 & SAB_ISR1_BRKT)
|
|
ipend |= UART_IPEND_BREAK;
|
|
if (isr0 & SAB_ISR0_RFO)
|
|
ipend |= UART_IPEND_OVERRUN;
|
|
if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
|
|
ipend |= UART_IPEND_RXREADY;
|
|
if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
|
|
ipend |= UART_IPEND_SIGCHG;
|
|
if (isr1 & SAB_ISR1_ALLS)
|
|
ipend |= UART_IPEND_TXIDLE;
|
|
|
|
return (ipend);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
mtx_lock_spin(&sc->sc_hwmtx);
|
|
error = sab82532_param(bas, baudrate, databits, stopbits, parity);
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_probe(struct uart_softc *sc)
|
|
{
|
|
char buf[80];
|
|
const char *vstr;
|
|
int error;
|
|
char ch;
|
|
|
|
error = sab82532_probe(&sc->sc_bas);
|
|
if (error)
|
|
return (error);
|
|
|
|
ch = sc->sc_bas.chan - 1 + 'A';
|
|
|
|
switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
|
|
case SAB_VSTR_V_1:
|
|
vstr = "v1";
|
|
break;
|
|
case SAB_VSTR_V_2:
|
|
vstr = "v2";
|
|
break;
|
|
case SAB_VSTR_V_32:
|
|
vstr = "v3.2";
|
|
sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
|
|
sc->sc_hwoflow = 1;
|
|
break;
|
|
default:
|
|
vstr = "v4?";
|
|
break;
|
|
}
|
|
|
|
snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
|
|
device_set_desc_copy(sc->sc_dev, buf);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int i, rbcl, xc;
|
|
uint8_t s;
|
|
|
|
bas = &sc->sc_bas;
|
|
mtx_lock_spin(&sc->sc_hwmtx);
|
|
if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
|
|
rbcl = uart_getreg(bas, SAB_RBCL) & 31;
|
|
if (rbcl == 0)
|
|
rbcl = 32;
|
|
for (i = 0; i < rbcl; i += 2) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
xc = uart_getreg(bas, SAB_RFIFO);
|
|
s = uart_getreg(bas, SAB_RFIFO + 1);
|
|
if (s & SAB_RSTAT_FE)
|
|
xc |= UART_STAT_FRAMERR;
|
|
if (s & SAB_RSTAT_PE)
|
|
xc |= UART_STAT_PARERR;
|
|
uart_rx_put(sc, xc);
|
|
}
|
|
}
|
|
|
|
while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
|
|
;
|
|
uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
|
|
uart_barrier(bas);
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
struct uart_bas *bas;
|
|
uint32_t new, old;
|
|
uint8_t mode, pvr;
|
|
|
|
bas = &sc->sc_bas;
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR,
|
|
SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS,
|
|
SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
|
|
mtx_lock_spin(&sc->sc_hwmtx);
|
|
/* Set DTR pin. */
|
|
pvr = uart_getreg(bas, SAB_PVR);
|
|
switch (bas->chan) {
|
|
case 1:
|
|
if (new & SER_DTR)
|
|
pvr &= ~SAB_PVR_DTR_A;
|
|
else
|
|
pvr |= SAB_PVR_DTR_A;
|
|
break;
|
|
case 2:
|
|
if (new & SER_DTR)
|
|
pvr &= ~SAB_PVR_DTR_B;
|
|
else
|
|
pvr |= SAB_PVR_DTR_B;
|
|
break;
|
|
}
|
|
uart_setreg(bas, SAB_PVR, pvr);
|
|
|
|
/* Set RTS pin. */
|
|
mode = uart_getreg(bas, SAB_MODE);
|
|
if (new & SER_RTS)
|
|
mode &= ~SAB_MODE_FRTS;
|
|
else
|
|
mode |= SAB_MODE_FRTS;
|
|
uart_setreg(bas, SAB_MODE, mode);
|
|
uart_barrier(bas);
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sab82532_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int i;
|
|
|
|
bas = &sc->sc_bas;
|
|
mtx_lock_spin(&sc->sc_hwmtx);
|
|
while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
|
|
;
|
|
for (i = 0; i < sc->sc_txdatasz; i++)
|
|
uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
|
|
uart_barrier(bas);
|
|
while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
|
|
;
|
|
uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
|
|
sc->sc_txbusy = 1;
|
|
mtx_unlock_spin(&sc->sc_hwmtx);
|
|
return (0);
|
|
}
|