05c62b81bf
the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
141 lines
4.4 KiB
C
141 lines
4.4 KiB
C
/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp
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* $FreeBSD$
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*/
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/*
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* Size of OpenPIC register space
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*/
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#define OPENPIC_SIZE 0x40000
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/*
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* Per Processor Registers [private access] (0x00000 - 0x00fff)
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*/
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/* IPI dispatch command reg */
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#define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10)
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/* current task priority reg */
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#define OPENPIC_TPR 0x80
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#define OPENPIC_TPR_MASK 0x0000000f
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#define OPENPIC_WHOAMI 0x90
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/* interrupt acknowledge reg */
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#define OPENPIC_IACK 0xa0
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/* end of interrupt reg */
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#define OPENPIC_EOI 0xb0
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/*
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* Global registers (0x01000-0x0ffff)
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*/
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/* feature reporting reg 0 */
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#define OPENPIC_FEATURE 0x1000
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#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff
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#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00
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#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8
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#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000
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#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16
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/* global config reg 0 */
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#define OPENPIC_CONFIG 0x1020
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#define OPENPIC_CONFIG_RESET 0x80000000
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#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000
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/* interrupt configuration mode (direct or serial) */
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#define OPENPIC_ICR 0x1030
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#define OPENPIC_ICR_SERIAL_MODE (1 << 27)
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#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28)
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#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28
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/* vendor ID */
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#define OPENPIC_VENDOR_ID 0x1080
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/* processor initialization reg */
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#define OPENPIC_PROC_INIT 0x1090
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/* IPI vector/priority reg */
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#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10)
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/* spurious intr. vector */
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#define OPENPIC_SPURIOUS_VECTOR 0x10e0
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/* Timer registers */
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#define OPENPIC_TIMERS 4
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#define OPENPIC_TFREQ 0x10f0
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#define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40)
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#define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40)
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#define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40)
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#define OPENPIC_TDST(t) (0x1130 + (t) * 0x40)
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/*
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* Interrupt Source Configuration Registers (0x10000 - 0x1ffff)
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*/
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/* interrupt vector/priority reg */
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#ifndef OPENPIC_SRC_VECTOR
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#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20)
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#endif
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#define OPENPIC_SENSE_LEVEL 0x00400000
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#define OPENPIC_SENSE_EDGE 0x00000000
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#define OPENPIC_POLARITY_POSITIVE 0x00800000
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#define OPENPIC_POLARITY_NEGATIVE 0x00000000
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#define OPENPIC_IMASK 0x80000000
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#define OPENPIC_ACTIVITY 0x40000000
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#define OPENPIC_PRIORITY_MASK 0x000f0000
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#define OPENPIC_PRIORITY_SHIFT 16
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#define OPENPIC_VECTOR_MASK 0x000000ff
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/* interrupt destination cpu */
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#ifndef OPENPIC_IDEST
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#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20)
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#endif
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/*
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* Per Processor Registers [global access] (0x20000 - 0x3ffff)
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*/
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#define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000)
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#define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \
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(OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi))
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#define OPENPIC_PCPU_TPR(cpu) \
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(OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR)
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#define OPENPIC_PCPU_WHOAMI(cpu) \
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(OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI)
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#define OPENPIC_PCPU_IACK(cpu) \
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(OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK)
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#define OPENPIC_PCPU_EOI(cpu) \
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(OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI)
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