8dd4275c36
with a ProATM-155 and an IDT evaluation board and should also work with a ProATM-25 (it seems to work at least, I cannot really measure what the card emits). The driver has been tested on i386 and sparc64, but should work an other archs also. It supports UBR, CBR, ABR and VBR; AAL0, AAL5 and AALraw. As an additional feature VCI/VPI 0/0 can be opened for receiving in AALraw mode and receives all cells not claimed by other open VCs (even cells with invalid GFC, VPI and VCI fields and OAM cells). Thanks to Christian Bucari from ProSum for lending two cards and answering my questions.
477 lines
18 KiB
C
477 lines
18 KiB
C
/*
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* Copyright (c) 2003
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* Fraunhofer Institute for Open Communication Systems (FhG Fokus).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Hartmut Brandt <harti@freebsd.org>
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*
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* $FreeBSD$
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*
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* Register definitions for the IDT77252 chip.
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*/
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#define PCI_VENDOR_IDT 0x111D
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#define PCI_DEVICE_IDT77252 3
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#define PCI_DEVICE_IDT77v252 4
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#define PCI_DEVICE_IDT77v222 5
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#define IDT_PCI_REG_MEMBASE 0x14
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#define IDT_NOR_D0 0x00 /* R/W Data register 0 */
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#define IDT_NOR_D1 0x04 /* R/W Data register 1 */
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#define IDT_NOR_D2 0x08 /* R/W Data register 2 */
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#define IDT_NOR_D3 0x0C /* R/W Data register 3 */
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#define IDT_NOR_CMD 0x10 /* R/W Command */
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#define IDT_NOR_CFG 0x14 /* R/W Configuration */
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#define IDT_NOR_STAT 0x18 /* R/W Status */
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#define IDT_NOR_RSQB 0x1C /* R/W Receive status queue base */
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#define IDT_NOR_RSQT 0x20 /* R Receive status queue tail */
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#define IDT_NOR_RSQH 0x24 /* R/W Receive status queue tail */
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#define IDT_NOR_CDC 0x28 /* R/W Cell drop counter */
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#define IDT_NOR_VPEC 0x2C /* R/W VPI/VCI Lookup error counter */
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#define IDT_NOR_ICC 0x30 /* R/W Invalid cell counter */
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#define IDT_NOR_RAWCT 0x34 /* R Raw cell tail */
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#define IDT_NOR_TMR 0x38 /* R Timer */
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#define IDT_NOR_TSTB 0x3C /* R/W Transmit schedule table base */
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#define IDT_NOR_TSQB 0x40 /* R/W Transmit Status queue base */
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#define IDT_NOR_TSQT 0x44 /* R/W Transmit Status queue tail */
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#define IDT_NOR_TSQH 0x48 /* R/W Transmit Status queue head */
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#define IDT_NOR_GP 0x4C /* R/W General purpose */
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#define IDT_NOR_VPM 0x50 /* R/W VPI/VCI mask */
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#define IDT_NOR_RXFD 0x54 /* R/W Receive FIFO descriptor */
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#define IDT_NOR_RXFT 0x58 /* R/W Receive FIFO tail */
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#define IDT_NOR_RXFH 0x5C /* R/W Receive FIFO head */
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#define IDT_NOR_RAWHND 0x60 /* R/W Raw cell handle */
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#define IDT_NOR_RXSTAT 0x64 /* R Receive connection state */
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#define IDT_NOR_ABRSTD 0x68 /* R/W ABR & VBR Schedule table descriptor */
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#define IDT_NOR_ABRRQ 0x6C /* R/W ABR Ready queue pointer */
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#define IDT_NOR_VBRRQ 0x70 /* R/W VBR Ready queue pointer */
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#define IDT_NOR_RTBL 0x74 /* R/W Rate table descriptor */
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#define IDT_NOR_MXDFCT 0x78 /* R/W Maximum deficit counter */
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#define IDT_NOR_TXSTAT 0x7C /* R/W Transmit connection state */
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#define IDT_NOR_TCMDQ 0x80 /* W Transmit command queue */
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#define IDT_NOR_IRCP 0x84 /* R/W Inactive receive connection pointer */
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#define IDT_NOR_FBQP0 0x88 /* R/W Free buffer queue 0 pointer */
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#define IDT_NOR_FBQP1 0x8C /* R/W Free buffer queue 1 pointer */
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#define IDT_NOR_FBQP2 0x90 /* R/W Free buffer queue 2 pointer */
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#define IDT_NOR_FBQP3 0x94 /* R/W Free buffer queue 3 pointer */
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#define IDT_NOR_FBQS0 0x98 /* R/W Free buffer queue 0 size */
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#define IDT_NOR_FBQS1 0x9C /* R/W Free buffer queue 1 size */
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#define IDT_NOR_FBQS2 0xA0 /* R/W Free buffer queue 2 size */
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#define IDT_NOR_FBQS3 0xA4 /* R/W Free buffer queue 3 size */
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#define IDT_NOR_FBQWP0 0xA8 /* R/W Free buffer queue 0 write pointer */
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#define IDT_NOR_FBQWP1 0xAC /* R/W Free buffer queue 1 write pointer */
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#define IDT_NOR_FBQWP2 0xB0 /* R/W Free buffer queue 2 write pointer */
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#define IDT_NOR_FBQWP3 0xB4 /* R/W Free buffer queue 3 write pointer */
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#define IDT_NOR_NOW 0xB8 /* R Current transmit schedule table addr */
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#define IDT_NOR_DNOW 0xBC /* R Dynamic Now register */
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#define IDT_NOR_END 0xC0
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/*
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* Command (IDT_NOR_CMD)
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*/
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#define IDT_CMD_NOP 0x00000000 /* No operation */
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#define IDT_CMD_OPCL 0x20000000 /* Open/Close connection */
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#define IDT_CMD_WSRAM 0x40000000 /* Write SRAM */
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#define IDT_CMD_RSRAM 0x50000000 /* Read SRAM */
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#define IDT_CMD_WFBQ 0x60000000 /* Write free buffer queue */
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#define IDT_CMD_RUTIL 0x80000000 /* Read utility bus */
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#define IDT_CMD_WUTIL 0x90000000 /* Write utility bus */
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#define IDT_MKCMD_OPEN(VC) (IDT_CMD_OPCL | (1 << 19) | ((V) << 4))
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#define IDT_MKCMD_CLOSE(VC) (IDT_CMD_OPCL | (0 << 19) | ((V) << 4))
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#define IDT_MKCMD_WSRAM(A, S) (IDT_CMD_WSRAM | ((A) << 2) | (S))
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#define IDT_MKCMD_RSRAM(A) (IDT_CMD_RSRAM | ((A) << 2))
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#define IDT_MKCMD_WFBQ(Q) (IDT_CMD_WFBQ | (Q))
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#define IDT_MKCMD_RUTIL(S0, S1, A) \
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(IDT_CMD_RUTIL | ((S1) << 9) | ((S0) << 8) | (A))
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#define IDT_MKCMD_WUTIL(S0, S1, A) \
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(IDT_CMD_WUTIL | ((S1) << 9) | ((S0) << 8) | (A))
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/*
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* Configuration register (CFG)
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*/
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#define IDT_CFG_SWRST 0x80000000 /* software reset */
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#define IDT_CFG_LOOP 0x40000000 /* internal loopback enable */
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#define IDT_CFG_RXPTH 0x20000000 /* receive path enable */
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#define IDT_CFG_IDLECLP 0x10000000 /* set CLP in null cells */
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#define IDT_CFG_TXFIFO9 0x00000000 /* Tx FIFO 9 cells */
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#define IDT_CFG_TXFIFO1 0x04000000 /* Tx FIFO 1 cells */
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#define IDT_CFG_TXFIFO2 0x08000000 /* Tx FIFO 2 cells */
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#define IDT_CFG_TXFIFO4 0x0C000000 /* Tx FIFO 4 cells */
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#define IDT_CFG_NOIDLE 0x02000000 /* don't send idle cells */
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#define IDT_CFG_RXQ128 0x00000000 /* Rx Status Queue 128 entries */
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#define IDT_CFG_RXQ256 0x00400000 /* Rx Status Queue 256 entries */
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#define IDT_CFG_RXQ512 0x00800000 /* Rx Status Queue 512 entries */
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#define IDT_CFG_ICAPT 0x00200000 /* Invalid cell accept */
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#define IDT_CFG_IGGFC 0x00100000 /* Ignore GFC field */
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#define IDT_CFG_VP0 0x00000000 /* 0 VPI bits */
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#define IDT_CFG_VP1 0x00040000 /* 1 VPI bit */
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#define IDT_CFG_VP2 0x00080000 /* 2 VPI bits */
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#define IDT_CFG_VP8 0x000C0000 /* 8 VPI bits */
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#define IDT_CFG_CTS1K 0x00000000 /* Rx Connection table 1024 entries */
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#define IDT_CFG_CTS4K 0x00010000 /* Rx Connection table 4096 entries */
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#define IDT_CFG_CTS16K 0x00020000 /* Rx Connection table 16384 entries */
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#define IDT_CFG_CTS512 0x00030000 /* Rx Connection table 512 entries */
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#define IDT_CFG_VPECA 0x00008000 /* VPI/VCI error cell accept */
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#define IDT_CFG_RXINONE 0x00000000 /* No interrupt on receive */
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#define IDT_CFG_RXIIMM 0x00001000 /* immediate interrupt */
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#define IDT_CFG_RXI28 0x00002000 /* every 0x2800 clocks */
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#define IDT_CFG_RXI4F 0x00003000 /* every 0x4F00 clocks */
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#define IDT_CFG_RXI74 0x00004000 /* every 0x7400 clocks */
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#define IDT_CFG_RAWIE 0x00000800 /* raw cell queue interrupt enable */
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#define IDT_CFG_RQFIE 0x00000400 /* Rx status queue almost full IE */
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#define IDT_CFG_CACHE 0x00000100 /* begin DMA on cache line */
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#define IDT_CFG_TIMOIE 0x00000080 /* timer roll over interrupt enable */
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#define IDT_CFG_FBIE 0x00000040 /* free buffer queue interrupt enable */
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#define IDT_CFG_TXENB 0x00000020 /* Tx enable */
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#define IDT_CFG_TXINT 0x00000010 /* Tx status interrupt enable */
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#define IDT_CFG_TXUIE 0x00000008 /* Tx underrun interrupt enable */
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#define IDT_CFG_UMODE 0x00000004 /* utopia byte mode */
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#define IDT_CFG_TXSFI 0x00000002 /* Tx status full interrupt enable */
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#define IDT_CFG_PHYIE 0x00000001 /* PHY interrupt enable */
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/*
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* Status register (STAT)
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*/
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#define IDT_STAT_FRAC3(S) (((S) >> 28) & 0xf) /* FBQ3 valid */
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#define IDT_STAT_FRAC2(S) (((S) >> 24) & 0xf) /* FBQ2 valid */
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#define IDT_STAT_FRAC1(S) (((S) >> 20) & 0xf) /* FBQ1 valid */
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#define IDT_STAT_FRAC0(S) (((S) >> 16) & 0xf) /* FBQ0 valid */
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#define IDT_STAT_TSIF 0x00008000 /* Tx status indicator flag */
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#define IDT_STAT_TXICP 0x00004000 /* Tx incomplete PDU */
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#define IDT_STAT_TSQF 0x00001000 /* Tx status queue full */
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#define IDT_STAT_TMROF 0x00000800 /* Timer overflow */
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#define IDT_STAT_PHYI 0x00000400 /* PHY interrupt */
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#define IDT_STAT_CMDBZ 0x00000200 /* command busy */
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#define IDT_STAT_FBQ3A 0x00000100 /* FBQ 3 attention flag */
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#define IDT_STAT_FBQ2A 0x00000080 /* FBQ 2 attention flag */
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#define IDT_STAT_RSQF 0x00000040 /* Rx status queue full */
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#define IDT_STAT_EPDU 0x00000020 /* end of CS-PDU */
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#define IDT_STAT_RAWCF 0x00000010 /* raw cell flag */
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#define IDT_STAT_FBQ1A 0x00000008 /* FBQ 1 attention flag */
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#define IDT_STAT_FBQ0A 0x00000004 /* FBQ 0 attention flag */
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#define IDT_STAT_RSQAF 0x00000002 /* Rx status queue almost full */
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/*
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* Cell drop count (CDC)
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*/
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#define IDT_CDC_RMID 0x00400000 /* RM cell ID error */
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#define IDT_CDC_CTE 0x00200000 /* Rx connection table error */
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#define IDT_CDC_NFB 0x00100000 /* No free buffers */
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#define IDT_CDC_OAMCRC 0x00080000 /* bad OAM CRC */
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#define IDT_CDC_RMCRC 0x00040000 /* bad RM CRC */
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#define IDT_CDC_RMFIFO 0x00020000 /* RM FIFO full */
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#define IDT_CDC_RXFIFO 0x00010000 /* Rx FIFO full */
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#define IDT_CDC(S) ((S) & 0xffff) /* cell drop counter */
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/*
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* VPI/VCI lookup error count (VPEC)
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*/
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#define IDT_VPEC(S) ((S) & 0xffff)
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/*
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* Invalid cell count (ICC)
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*/
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#define IDT_ICC(S) ((S) & 0xffff)
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/*
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* General purpose register
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*/
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#define IDT_GP_TXNCC(S) (((S) >> 24) & 0xff) /* Tx negative cell count */
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#define IDT_GP_EEDI 0x00010000 /* EEPROM data in */
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#define IDT_GP_BIGE 0x00008000 /* big endian enable */
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#define IDT_GP_RM 0x00000000 /* process RM cells */
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#define IDT_GP_RM_TEE 0x00002000 /* process RM cells and put in RawQ */
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#define IDT_GP_RM_RAW 0x00006000 /* put RM cells in RawQ */
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#define IDT_GP_DLOOP 0x00001000 /* double loopback */
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#define IDT_GP_PCIPAR 0x00000010 /* force PCI parity error */
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#define IDT_GP_PCIPERR 0x00000020 /* force PERR */
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#define IDT_GP_PCISERR 0x00000040 /* force SERR */
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#define IDT_GP_PHY_RST 0x00000008 /* PHY reset */
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#define IDT_GP_EESCLK 0x00000004 /* EEPROM clock */
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#define IDT_GP_EECS 0x00000002 /* EEPROM chip select */
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#define IDT_GP_EEDO 0x00000001 /* EEPROM data out */
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/*
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* Receive FIFO descriptor register (RXFD)
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*/
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#define IDT_RXFD(A, S) (((S) << 24) | ((A) << 2))
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#define IDT_RXFDS(V) (((V) >> 24) & 0xf)
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#define IDT_RXFDA(V) (((V) & 0x1ffffc) >> 2)
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/*
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* ABR & VBR schedule table descriptor register
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*/
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#define IDT_ABRSTD(A, S) (((S) << 24) | ((A) << 2))
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#define IDT_ABRSTDS(V) (((V) >> 24) & 0x7)
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#define IDT_ABRSTDA(V) (((V) & 0x1ffffc) >> 2)
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/*
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* ABR/VBR ready queue register
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*/
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#define IDT_ABRRQH(V) (((V) >> 16) & 0x3fff)
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#define IDT_ABRRQT(V) (((V) >> 0) & 0x3fff)
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#define IDT_VBRRQH(V) (((V) >> 16) & 0x3fff)
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#define IDT_VBRRQT(V) (((V) >> 0) & 0x3fff)
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/*
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* Maximum deficit limit register
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*/
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#define IDT_MDFCT_LCI 0x00020000 /* local congestion indicator enable */
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#define IDT_MDFCT_LNI 0x00010000 /* local no incread enable */
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/*
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* Transmit command queue register
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*/
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#define IDT_TCMDQ_NOP() ((0x0 << 24)) /* no operation */
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#define IDT_TCMDQ_START(C) ((0x1 << 24) | (C)) /* start connection */
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#define IDT_TCMDQ_ULACR(C, L) ((0x2 << 24) | (C) | ((L) << 16))
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/* update LACR */
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#define IDT_TCMDQ_SLACR(C, L) ((0x3 << 24) | (C) | ((L) << 16))
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/* start and update LACR */
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#define IDT_TCMDQ_UIER(C, L) ((0x4 << 24) | (C) | ((L) << 16))
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/* update Int ER */
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#define IDT_TCMDQ_HALT(C) ((0x5 << 24) | (C)) /* halt connection */
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/*
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* Free buffer queue size registers
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*/
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#define IDT_FBQS(T, N, C, S) (((T) << 28) | ((N) << 24) | ((C) << 20) | (S))
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/*
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* Receive status queue
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*/
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struct idt_rsqe {
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uint32_t cid; /* VPI/VCI */
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uint32_t handle; /* buffer handle */
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uint32_t crc; /* AAL-5 CRC */
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uint32_t stat; /* div. flags */
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};
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#define IDT_RSQE_SIZE 16 /* bytes */
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#define IDT_RSQE_VPI(CID) (((CID) >> 16) & 0xff)
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#define IDT_RSQE_VCI(CID) ((CID) & 0xffff)
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#define IDT_RSQE_TYPE(S) (((S) >> 30) & 0x3)
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#define IDT_RSQE_DATA 0x2
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#define IDT_RSQE_IDLE 0x3
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#define IDT_RSQE_VALID 0x80000000
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#define IDT_RSQE_POOL(S) (((S) >> 16) & 0x3)
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#define IDT_RSQE_BUF 0x8000
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#define IDT_RSQE_NZGFC 0x4000
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#define IDT_RSQE_EPDU 0x2000
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#define IDT_RSQE_CBUF 0x1000
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#define IDT_RSQE_EFCIE 0x0800
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#define IDT_RSQE_CLP 0x0400
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#define IDT_RSQE_CRC 0x0200
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#define IDT_RSQE_CNT(S) ((S) & 0x1ff)
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#define IDT_RSQH(R) (((R) & 0x1ffc) >> 2)
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#define IDT_RSQT(R) (((R) & 0x1ffc) >> 2)
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/*
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* Transmit status queue
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*/
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#define IDT_TSQ_SIZE 1024 /* no. of entries */
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#define IDT_TSQE_SIZE 8 /* bytes */
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#define IDT_TSQE_SHIFT 3
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struct idt_tsqe {
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uint32_t stat;
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uint32_t stamp;
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};
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#define IDT_TSQE_EMPTY 0x80000000
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#define IDT_TSQE_TYPE(E) (((E) >> 29) & 0x3)
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#define IDT_TSQE_TIMER 0x0
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#define IDT_TSQE_TSR 0x1
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#define IDT_TSQE_IDLE 0x2
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#define IDT_TSQE_TBD 0x3
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#define IDT_TSQE_TAG(E) (((E) >> 24) & 0x1f)
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#define IDT_TSQE_HALTED 0x10
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#define IDT_TSQE_STAMP(E) ((E) & 0xffffff)
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#define IDT_TSQE_TAG_SPACE 32
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/*
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* Raw cell handle
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*/
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struct idt_rawhnd {
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uint32_t tail;
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uint32_t handle;
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};
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#define IDT_RAWHND_SIZE 8
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/*
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* TST
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*/
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#define IDT_TST_NULL (0 << 29) /* transmit NULL cell */
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#define IDT_TST_CBR (1 << 29) /* transmit CBR cell */
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#define IDT_TST_VBR (2 << 29) /* transmit [AVU]BR cell */
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#define IDT_TST_BR (3 << 29) /* branch */
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#define IDT_TST_MASK 0x7ffff
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/*
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* Free buffer queue
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*/
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#define IDT_FBQ_SIZE 512 /* entries */
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/*
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* Receive connection table
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*/
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#define IDT_RCT_FBP2 0x00400000 /* use FBQ 2 */
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#define IDT_RCT_OPEN 0x00080000 /* connection open */
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#define IDT_RCT_AAL0 0x00000000 /* AAL 0 */
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#define IDT_RCT_AAL34 0x00010000 /* AAL 3/4 */
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#define IDT_RCT_AAL5 0x00020000 /* AAL 5 */
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#define IDT_RCT_AALRAW 0x00030000 /* raw cells */
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#define IDT_RCT_AALOAM 0x00040000 /* OAM cells */
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#define IDT_RCT_RCI 0x00008000 /* raw cell interrupt enable */
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#define IDT_RCT_IACT_CNT_MASK 0x1c000000
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#define IDT_RCT_IACT_CNT_SHIFT 26
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#define IDT_RCT_ENTRY_SIZE 4 /* words */
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/*
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* Transmit connection table
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*/
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#define IDT_TCT_CBR 0x00000000
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#define IDT_TCT_VBR 0x40000000
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#define IDT_TCT_ABR 0x80000000
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#define IDT_TCT_UBR 0x00000000
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#define IDT_TCT_UBR_FLG 0x80000000 /* word8 flag */
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#define IDT_TCT_HALT 0x80000000 /* connection halted */
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#define IDT_TCT_IDLE 0x40000000 /* connection idle */
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#define IDT_TCT_TSIF 0x00004000
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#define IDT_TCT_MAXIDLE 0x7f000000
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#define IDT_TCT_MBS_SHIFT 16
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#define IDT_TCT_CRM_SHIFT 29
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#define IDT_TCT_NAGE_SHIFT 21
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#define IDT_TCT_LMCR_SHIFT 24
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#define IDT_TCT_CDF_SHIFT 20
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#define IDT_TCT_RDF_SHIFT 14
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#define IDT_TCT_AIR_SHIFT 8
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#define IDT_TCT_ACRI_SHIFT 16
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/*
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* Segmentation channel queue
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*/
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#define IDT_SCQ_SIZE 64 /* number of entries */
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struct idt_tbd {
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uint32_t flags;
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uint32_t addr;
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uint32_t aal5;
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uint32_t hdr;
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};
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#define IDT_TBD_SIZE 16 /* bytes */
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#define IDT_TBD_SHIFT 4
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#define IDT_TBD_TSR 0x80000000 /* TSR entry */
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#define IDT_TBD_EPDU 0x40000000 /* end of AAL PDU */
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#define IDT_TBD_TSIF 0x20000000 /* generate status */
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#define IDT_TBD_AAL0 0x00000000 /* AAL0 */
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#define IDT_TBD_AAL34 0x04000000 /* AAL3/4 */
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#define IDT_TBD_AAL5 0x08000000 /* AAL5 */
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#define IDT_TBD_AALOAM 0x10000000 /* OAM cells */
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#define IDT_TBD_GTSI 0x02000000 /* generate transmit status entry */
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#define IDT_TBD_TAG_SHIFT 20
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#define IDT_TBD_HDR(VPI, VCI, PTI, CLP) \
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(((VPI) << 20) | ((VCI) << 4) | ((PTI) << 1) | (CLP))
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#define IDT_TBD_VPI(H) (((H) >> 20) & 0xff)
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#define IDT_TBD_VCI(H) (((H) >> 4) & 0xffff)
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/*
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* Segmentation channel descriptor
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*/
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#define IDT_SCD_SIZE 12 /* words */
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/*
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* Memory map for the different RAM sizes
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*
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* 16k 32k 128k 512k
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*
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* TxCT 0x00000/4k 0x00000/8x 0x00000/32k 0x00000/128k
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* RxCT 0x01000/2k 0x02000/4k 0x08000/16k 0x20000/64k
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* FBQ0 0x01800/1k 0x03000/1k 0x0c000/1k 0x30000/1k
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* FBQ1 0x01c00/1k 0x03400/1k 0x0c400/1k 0x30400/1k
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* FBQ2 0x02000/1k 0x03800/1k 0x0c800/1k 0x30800/1k
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* FBQ3 - - - -
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* RT 0x02400/4.5k 0x03c00/4.5k 0x0cc00/4.5k 0x30c00/4.5k
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* SCD 0x03600/597 0x04e00/1621 0x0de00/9358 0x31e00/43036
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* TST 0x06000/2x2k 0x0c000/2x4k 0x37000/2x8k 0xef000/2x16k
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* ABR ST 0x07000/2x1k 0x0e000/2x2k 0x3b000/2x8k 0xf7000/2x16k
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* RxFIFO 0x07800/2k 0x0f000/4k 0x3f000/4k 0xff000/4k
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* End 0x08000 0x10000 0x40000 0x100000
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*/
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struct idt_mmap {
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u_int sram; /* K SRAM */
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u_int max_conn; /* connections */
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u_int vcbits; /* VPI + VCI bits */
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u_int rxtab; /* CFG word for CNTBL field */
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u_int rct; /* RCT base */
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u_int rtables; /* rate table address */
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u_int scd_base; /* SCD area base address */
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u_int scd_num; /* number of SCDs */
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u_int tst1base; /* base address of TST 1 */
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u_int tst_size; /* TST size in words */
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u_int abrstd_addr; /* schedule table address */
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u_int abrstd_size; /* schedule table size */
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u_int abrstd_code; /* schedule table size */
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u_int rxfifo_addr; /* address */
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u_int rxfifo_size; /* in words */
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u_int rxfifo_code; /* size */
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};
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#define IDT_MMAP { \
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{ /* 16k x 32, 512 connections */ \
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16, 512, 9, IDT_CFG_CTS512, /* RAM, connections, VC bits */ \
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0x01000, /* RCT base */ \
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0x02400, /* rate table address */ \
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0x03600, 597, /* SCD base and num */ \
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0x06000, 2048, /* TST/words, base */ \
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0x07000, 2048, 0x1, /* ABR schedule table */ \
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0x07800, 2048, 0x2 /* RxFIFO size in words */ \
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}, \
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{ /* 32k x 32, 1024 connections */ \
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32, 1024, 10, IDT_CFG_CTS1K, /* RAM, connections, VC bits */ \
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0x02000, /* RCT base */ \
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0x03c00, /* rate table address */ \
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0x04e00, 1621, /* SCD base and num */ \
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0x0c000, 4096, /* TST/words, base */ \
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0x0e000, 4096, 0x2, /* ABR schedule table */ \
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0x0f000, 4096, 0x3 /* RxFIFO size in words */ \
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}, \
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{ /* 128k x 32, 4096 connections */ \
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128, 4096, 12, IDT_CFG_CTS4K, /* RAM, connections, VC bits */ \
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0x08000, /* RCT base */ \
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0x0cc00, /* rate table address */ \
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0x0de00, 9358, /* SCD base and num */ \
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0x37000, 8192, /* TST/words, base */ \
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0x3b000, 16384, 0x4, /* ABR schedule table */ \
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0x3f000, 4096, 0x3 /* RxFIFO size in words */ \
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}, \
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{ /* 512k x 32, 512 connections */ \
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512, 16384, 14, IDT_CFG_CTS16K, /* RAM, connections, VC bits */\
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0x20000, /* RCT base */ \
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0x30c00, /* rate table address */ \
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0x31e00, 43036, /* SCD base and num */ \
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0xef000, 16384, /* TST/words, base */ \
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0xf7000, 16384, 0x5, /* ABR schedule table */ \
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0xff000, 4096, 0x3 /* RxFIFO size in words */ \
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}, \
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}
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