272489fe59
the implementation can guarantee forward progress in the event of a stuck interrupt or interrupt storm. This is especially critical for fast interrupt handlers, as they can cause a hard hang in that case. When first called, arm_get_next_irq() is passed -1. Obtained from: Juniper Networks, Inc.
251 lines
8.1 KiB
C
251 lines
8.1 KiB
C
/* $NetBSD: i80321.c,v 1.15 2003/10/06 16:06:05 thorpej Exp $ */
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/*-
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Autoconfiguration support for the Intel i80321 I/O Processor.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/xscale/i80321/i80321reg.h>
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#include <arm/xscale/i80321/i80321var.h>
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#include <arm/xscale/i80321/i80321_intr.h>
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#include <dev/pci/pcireg.h>
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volatile uint32_t intr_enabled;
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uint32_t intr_steer = 0;
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/*
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* Statically-allocated bus_space stucture used to access the
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* i80321's own registers.
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*/
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struct bus_space i80321_bs_tag;
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/*
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* There can be only one i80321, so we keep a global pointer to
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* the softc, so board-specific code can use features of the
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* i80321 without having to have a handle on the softc itself.
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*/
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struct i80321_softc *i80321_softc;
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#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
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/*
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* i80321_attach:
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*
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* Board-independent attach routine for the i80321.
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*/
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void
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i80321_attach(struct i80321_softc *sc)
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{
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i80321_softc = sc;
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uint32_t preg;
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/* We expect the Memory Controller to be already sliced off. */
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/*
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* Program the Inbound windows.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0,
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(0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0,
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sc->sc_iwin[0].iwin_xlate);
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_BARS, sc->sc_iwin[0].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_BARS + 0x04, sc->sc_iwin[0].iwin_base_hi);
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} else {
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sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, PCIR_BARS);
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sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, PCIR_BARS + 0x04);
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sc->sc_iwin[0].iwin_base_lo =
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PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
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(0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
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/* no xlate for window 1 */
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_BARS + 0x08, sc->sc_iwin[1].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_BARS + 0x0c, sc->sc_iwin[1].iwin_base_hi);
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} else {
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sc->sc_iwin[1].iwin_base_lo = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, PCIR_BARS + 0x08);
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sc->sc_iwin[1].iwin_base_hi = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, PCIR_BARS + 0x0c);
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sc->sc_iwin[1].iwin_base_lo =
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PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2,
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(0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2,
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sc->sc_iwin[2].iwin_xlate);
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_BARS + 0x10, sc->sc_iwin[2].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_BARS + 0x14, sc->sc_iwin[2].iwin_base_hi);
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} else {
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sc->sc_iwin[2].iwin_base_lo = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, PCIR_BARS + 0x10);
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sc->sc_iwin[2].iwin_base_hi = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, PCIR_BARS + 0x14);
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sc->sc_iwin[2].iwin_base_lo =
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PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3,
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(0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3,
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sc->sc_iwin[3].iwin_xlate);
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
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} else {
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sc->sc_iwin[3].iwin_base_lo = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, ATU_IABAR3);
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sc->sc_iwin[3].iwin_base_hi = bus_space_read_4(sc->sc_st,
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sc->sc_atu_sh, ATU_IAUBAR3);
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sc->sc_iwin[3].iwin_base_lo =
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PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo);
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}
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/*
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* Mask (disable) the ATU interrupt sources.
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* XXX May want to revisit this if we encounter
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* XXX an application that wants it.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_ATUIMR,
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ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST|
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ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM|
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ATUIMR_PTAT|ATUIMR_PMPE);
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/*
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* Program the outbound windows.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OIOWTVR, sc->sc_ioout_xlate);
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if (!sc->sc_is_host) {
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sc->sc_owin[0].owin_xlate_lo = sc->sc_iwin[1].iwin_base_lo;
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sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi);
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/*
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* Set up the ATU configuration register. All we do
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* right now is enable Outbound Windows.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR,
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ATUCR_OUT_EN);
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/*
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* Enable bus mastering, memory access, SERR, and parity
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* checking on the ATU.
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*/
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if (sc->sc_is_host) {
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preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_COMMAND);
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preg |= PCIM_CMD_MEMEN |
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PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
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PCIM_CMD_SERRESPEN;
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCIR_COMMAND, preg);
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}
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/* Initialize the bus space tags. */
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i80321_io_bs_init(&sc->sc_pci_iot, sc);
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i80321_mem_bs_init(&sc->sc_pci_memt, sc);
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intr_enabled = 0;
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i80321_set_intrmask();
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i80321_set_intrsteer();
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}
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static __inline uint32_t
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i80321_iintsrc_read(void)
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{
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uint32_t iintsrc;
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__asm __volatile("mrc p6, 0, %0, c8, c0, 0"
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: "=r" (iintsrc));
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/*
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* The IINTSRC register shows bits that are active even
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* if they are masked in INTCTL, so we have to mask them
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* off with the interrupts we consider enabled.
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*/
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return (iintsrc & intr_enabled);
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}
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int
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arm_get_next_irq(int last __unused)
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{
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int irq;
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if ((irq = i80321_iintsrc_read()))
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return (ffs(irq) - 1);
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return (-1);
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}
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