86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
/*-
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* Copyright (C) 2008 Semihalf, Rafal Jaworowski
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* Copyright 2006 by Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MPC85XX_H_
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#define _MPC85XX_H_
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/*
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* Configuration control and status registers
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*/
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#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
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#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
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/*
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* E500 Coherency Module registers
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*/
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#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
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/*
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* Local access registers
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*/
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#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n))
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#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n))
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#define OCP85XX_TGTIF_LBC 4
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#define OCP85XX_TGTIF_RAM_INTL 11
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#define OCP85XX_TGTIF_RIO 12
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#define OCP85XX_TGTIF_RAM1 15
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#define OCP85XX_TGTIF_RAM2 22
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/*
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* L2 cache registers
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*/
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#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
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/*
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* Power-On Reset configuration
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*/
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#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
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#define OCP85XX_PORDEVSR_IO_SEL 0x00780000
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#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
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#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
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/*
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* Status Registers.
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*/
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#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
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/*
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* Prototypes.
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*/
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uint32_t ccsr_read4(uintptr_t addr);
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void ccsr_write4(uintptr_t addr, uint32_t val);
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int law_enable(int trgt, u_long addr, u_long size);
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int law_disable(int trgt, u_long addr, u_long size);
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int law_getmax(void);
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int law_pci_target(struct resource *, int *, int *);
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#endif /* _MPC85XX_H_ */
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