a7a0fa5f58
- Centralize PCI resource allocation/release. - Enable flowid (TSS) support. - Added "per-fastpath" locks and watchdog timeouts. - Fixed problem where the CQ producer index was advanced beyond the size of the CQ ring during initialization. - Replaced hard-coded debug levels in some debug print statements. - More style(9) fixes. MFC after: Two weeks
164 lines
5.1 KiB
C
164 lines
5.1 KiB
C
/*-
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* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
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*
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* Gary Zambrano <zambrano@broadcom.com>
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* David Christensen <davidch@broadcom.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Broadcom Corporation nor the name of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written consent.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef _BXE_INCLUDE_H
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#define _BXE_INCLUDE_H
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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/*
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* Convert FreeBSD byte order to match generated code usage.
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*/
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#if BYTE_ORDER == BIG_ENDIAN
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#define __BIG_ENDIAN 1
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#undef __LITTLE_ENDIAN
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#else
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#undef __BIG_ENDIAN
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#define __LITTLE_ENDIAN 1
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#endif
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#include "bxe_debug.h"
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#include "bxe_reg.h"
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#include "bxe_fw_defs.h"
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#include "bxe_hsi.h"
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#include "bxe_link.h"
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/*
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* Convenience definitions used in multiple files.
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*/
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#define BXE_PRINTF(fmt, args...) \
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do { \
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device_printf(sc->dev, fmt, ##args); \
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}while(0)
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#ifdef BXE_DEBUG
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#define REG_WR(sc, offset, val) \
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bxe_reg_write32(sc, offset, val)
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#define REG_WR8(sc, offset, val) \
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bxe_reg_write8(sc, offset, val)
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#define REG_WR16(sc, offset, val) \
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bxe_reg_write16(sc, offset, val)
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#define REG_WR32(sc, offset, val) \
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bxe_reg_write32(sc, offset, val)
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#define REG_RD(sc, offset) \
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bxe_reg_read32(sc, offset)
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#define REG_RD8(sc, offset) \
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bxe_reg_read8(sc, offset)
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#define REG_RD16(sc, offset) \
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bxe_reg_read16(sc, offset)
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#define REG_RD32(sc, offset) \
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bxe_reg_read32(sc, offset)
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#define REG_RD_IND(sc, offset) \
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bxe_reg_rd_ind(sc, offset)
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#define REG_WR_IND(sc, offset, val) \
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bxe_reg_wr_ind(sc, offset, val)
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#else
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#define REG_WR(sc, offset, val) \
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bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
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#define REG_WR8(sc, offset, val) \
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bus_space_write_1(sc->bxe_btag, sc->bxe_bhandle, offset, val)
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#define REG_WR16(sc, offset, val) \
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bus_space_write_2(sc->bxe_btag, sc->bxe_bhandle, offset, val)
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#define REG_WR32(sc, offset, val) \
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bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
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#define REG_RD(sc, offset) \
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bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
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#define REG_RD8(sc, offset) \
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bus_space_read_1(sc->bxe_btag, sc->bxe_bhandle, offset)
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#define REG_RD16(sc, offset) \
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bus_space_read_2(sc->bxe_btag, sc->bxe_bhandle, offset)
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#define REG_RD32(sc, offset) \
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bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
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#define REG_RD_IND(sc, offset) \
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bxe_reg_rd_ind(sc, offset)
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#define REG_WR_IND(sc, offset, val) \
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bxe_reg_wr_ind(sc, offset, val)
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#endif /* BXE_DEBUG */
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#define REG_RD_DMAE(sc, offset, val, len32) \
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do { \
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bxe_read_dmae(sc, offset, len32); \
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memcpy(val, BXE_SP(sc, wb_data[0]), len32 * 4); \
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} while (0)
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#define REG_WR_DMAE(sc, offset, val, len32) \
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do { \
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memcpy(BXE_SP(sc, wb_data[0]), val, len32 * 4); \
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bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), \
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offset, len32); \
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} while (0)
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#define SHMEM_ADDR(sc, field) (sc->common.shmem_base + \
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offsetof(struct shmem_region, field))
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#define SHMEM_RD(sc, field) \
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REG_RD(sc, SHMEM_ADDR(sc, field))
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#define SHMEM_RD16(sc, field) \
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REG_RD16(sc, SHMEM_ADDR(sc, field))
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#define SHMEM_WR(sc, field, val) \
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REG_WR(sc, SHMEM_ADDR(sc, field), val)
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#define SHMEM2_ADDR(sc, field) (sc->common.shmem2_base + \
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offsetof(struct shmem2_region, field))
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#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
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#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
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#define EMAC_RD(sc, reg) \
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REG_RD(sc, emac_base + (uint32_t) reg)
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#define EMAC_WR(sc, reg, val) \
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REG_WR(sc, emac_base + (uint32_t) reg, val)
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#define BMAC_WR(sc, reg, val) \
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REG_WR(sc, GRCBASE_NIG + bmac_addr + reg, val)
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#endif /* _BXE_INCLUDE_H */
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