29332c0dce
This adds support for the IPQ4018/IPQ4019 MDIO bus. This is used to talk to external PHYs and switches. (There's an internal switch in the IPQ4018/IPQ4019 as well, but it's accessible via MMIO/AXI.) Differential Revision: https://reviews.freebsd.org/D34110 Reviewed by: manu
299 lines
7.5 KiB
C
299 lines
7.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This is the MDIO controller for the IPQ4018/IPQ4019.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "mdio_if.h"
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#include <dev/qcom_mdio/qcom_mdio_ipq4018_var.h>
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#include <dev/qcom_mdio/qcom_mdio_ipq4018_reg.h>
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#include <dev/qcom_mdio/qcom_mdio_debug.h>
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static int
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qcom_mdio_ipq4018_probe(device_t dev)
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{
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if (! ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "qcom,ipq4019-mdio") == 0)
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return (ENXIO);
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device_set_desc(dev,
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"Qualcomm Atheros IPQ4018/IPQ4019 MDIO driver");
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return (0);
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}
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static int
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qcom_mdio_ipq4018_detach(device_t dev)
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{
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struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
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if (sc->sc_mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
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sc->sc_mem_res);
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mtx_destroy(&sc->sc_mtx);
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return (0);
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}
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static void
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qcom_mdio_sysctl_attach(struct qcom_mdio_ipq4018_softc *sc)
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{
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struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
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struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"debug", CTLFLAG_RW, &sc->sc_debug, 0,
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"control debugging printfs");
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}
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static int
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qcom_mdio_ipq4018_attach(device_t dev)
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{
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phandle_t node;
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struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
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int error = 0;
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node = ofw_bus_get_node(dev);
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sc->sc_dev = dev;
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sc->sc_debug = 0;
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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/*
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* Map the MDIO memory region.
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*/
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sc->sc_mem_rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->sc_mem_rid, RF_ACTIVE);
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if (sc->sc_mem_res == NULL) {
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error = ENXIO;
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device_printf(dev, "%s: failed to map device memory\n",
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__func__);
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goto error;
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}
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sc->sc_mem_res_size = (size_t) bus_get_resource_count(dev,
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SYS_RES_MEMORY, sc->sc_mem_rid);
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if (sc->sc_mem_res_size == 0) {
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error = ENXIO;
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device_printf(dev, "%s: failed to get device memory size\n",
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__func__);
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goto error;
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}
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qcom_mdio_sysctl_attach(sc);
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OF_device_register_xref(OF_xref_from_node(node), dev);
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return (0);
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error:
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if (sc->sc_mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
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sc->sc_mem_res);
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mtx_destroy(&sc->sc_mtx);
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return (error);
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}
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/*
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* Wait for the BUSY flag to become zero.
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*
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* This has to happen before every MDIO transfer.
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*
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* Returns 0 if OK, error if error/timed out.
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*/
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static int
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qcom_mdio_ipq4018_wait(struct qcom_mdio_ipq4018_softc *sc)
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{
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int i;
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uint32_t reg;
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MDIO_LOCK_ASSERT(sc);
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for (i = 0; i < QCOM_IPQ4018_MDIO_SLEEP_COUNT; i++) {
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MDIO_BARRIER_READ(sc);
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reg = MDIO_READ(sc, QCOM_IPQ4018_MDIO_REG_CMD);
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if ((reg & QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_BUSY) == 0)
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return (0);
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DELAY(QCOM_IPQ4018_MDIO_SLEEP);
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}
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device_printf(sc->sc_dev, "%s: warning: timeout waiting for bus\n",
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__func__);
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return (ETIMEDOUT);
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}
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static void
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qcom_mdio_ipq4018_set_phy_reg_addr(struct qcom_mdio_ipq4018_softc *sc,
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int phy, int reg)
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{
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MDIO_LOCK_ASSERT(sc);
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MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_ADDR,
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((phy & 0xff) << 8) | (reg & 0xff));
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MDIO_BARRIER_WRITE(sc);
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}
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static int
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qcom_mdio_ipq4018_readreg(device_t dev, int phy, int reg)
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{
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struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
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uint32_t ret;
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QCOM_MDIO_DPRINTF(sc, QCOM_MDIO_DEBUG_REG_READ,
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"%s: called; phy=0x%x reg=0x%x\n",
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__func__, phy, reg);
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MDIO_LOCK(sc);
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if (qcom_mdio_ipq4018_wait(sc) != 0) {
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MDIO_UNLOCK(sc);
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return (-1);
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}
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/* Set phy/reg values */
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qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);
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/* Issue read command */
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MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_CMD,
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QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_START |
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QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_READ);
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MDIO_BARRIER_WRITE(sc);
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/* Wait for completion */
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if (qcom_mdio_ipq4018_wait(sc) != 0) {
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MDIO_UNLOCK(sc);
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return (-1);
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}
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/* Fetch return register value */
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MDIO_BARRIER_READ(sc);
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ret = MDIO_READ(sc, QCOM_IPQ4018_MDIO_REG_READ);
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MDIO_UNLOCK(sc);
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QCOM_MDIO_DPRINTF(sc, QCOM_MDIO_DEBUG_REG_READ,
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"%s: -> 0x%x\n", __func__, ret);
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return (ret);
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}
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static int
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qcom_mdio_ipq4018_writereg(device_t dev, int phy, int reg, int value)
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{
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struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
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QCOM_MDIO_DPRINTF(sc, QCOM_MDIO_DEBUG_REG_WRITE,
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"%s: called; phy=0x%x reg=0x%x val=0x%x\n",
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__func__, phy, reg, value);
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MDIO_LOCK(sc);
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if (qcom_mdio_ipq4018_wait(sc) != 0) {
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MDIO_UNLOCK(sc);
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return (-1);
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}
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/* Set phy/reg values */
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qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);
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/* Write command */
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MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_WRITE, value);
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MDIO_BARRIER_WRITE(sc);
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/* Issue write command */
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MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_CMD,
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QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_START |
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QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_WRITE);
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MDIO_BARRIER_WRITE(sc);
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/* Wait for completion */
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if (qcom_mdio_ipq4018_wait(sc) != 0) {
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MDIO_UNLOCK(sc);
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return (-1);
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}
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MDIO_UNLOCK(sc);
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return (0);
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}
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static device_method_t qcom_mdio_ipq4018_methods[] = {
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/* Driver */
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DEVMETHOD(device_probe, qcom_mdio_ipq4018_probe),
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DEVMETHOD(device_attach, qcom_mdio_ipq4018_attach),
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DEVMETHOD(device_detach, qcom_mdio_ipq4018_detach),
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/* MDIO interface */
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DEVMETHOD(mdio_readreg, qcom_mdio_ipq4018_readreg),
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DEVMETHOD(mdio_writereg, qcom_mdio_ipq4018_writereg),
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{0, 0},
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};
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static driver_t qcom_mdio_ipq4018_driver = {
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"mdio",
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qcom_mdio_ipq4018_methods,
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sizeof(struct qcom_mdio_ipq4018_softc),
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};
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static devclass_t qcom_mdio_ipq4018_devclass;
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EARLY_DRIVER_MODULE(qcom_mdio_ipq4018, simplebus, qcom_mdio_ipq4018_driver,
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qcom_mdio_ipq4018_devclass, NULL, 0,
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BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_LATE);
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MODULE_DEPEND(qcom_mdio_ipq4018, ether, 1, 1, 1);
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MODULE_DEPEND(qcom_mdio_ipq4018, mdio, 1, 1, 1);
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MODULE_DEPEND(qcom_mdio_ipq4018, miibus, 1, 1, 1);
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MODULE_VERSION(qcom_mdio_ipq4018, 1);
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