29332c0dce
This adds support for the IPQ4018/IPQ4019 MDIO bus. This is used to talk to external PHYs and switches. (There's an internal switch in the IPQ4018/IPQ4019 as well, but it's accessible via MMIO/AXI.) Differential Revision: https://reviews.freebsd.org/D34110 Reviewed by: manu
69 lines
2.6 KiB
C
69 lines
2.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QCOM_MDIO_IPQ4018_VAR_H__
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#define __QCOM_MDIO_IPQ4018_VAR_H__
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#define MDIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define MDIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define MDIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define MDIO_WRITE(sc, reg, val) do { \
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bus_write_4(sc->sc_mem_res, (reg), (val)); \
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} while (0)
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#define MDIO_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))
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#define MDIO_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, \
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0, (sc)->sc_mem_res_size, BUS_SPACE_BARRIER_WRITE)
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#define MDIO_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, \
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0, (sc)->sc_mem_res_size, BUS_SPACE_BARRIER_READ)
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#define MDIO_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, \
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0, (sc)->sc_mem_res_size, \
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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#define MDIO_SET_BITS(sc, reg, bits) \
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GPIO_WRITE(sc, reg, MDIO_READ(sc, (reg)) | (bits))
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#define MDIO_CLEAR_BITS(sc, reg, bits) \
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GPIO_WRITE(sc, reg, MDIO_READ(sc, (reg)) & ~(bits))
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struct qcom_mdio_ipq4018_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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struct resource *sc_mem_res;
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size_t sc_mem_res_size;
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int sc_mem_rid;
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uint32_t sc_debug;
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};
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#endif /* __QCOM_MDIO_IPQ4018_VAR_H__ */
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