96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
/*-
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* Copyright (c) 2014 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <machine/armreg.h>
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#include <stand.h>
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#include <efi.h>
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#include "cache.h"
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static unsigned int
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get_dcache_line_size(void)
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{
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uint64_t ctr;
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unsigned int dcl_size;
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/* Accessible from all security levels */
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ctr = READ_SPECIALREG(ctr_el0);
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/*
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* Relevant field [19:16] is LOG2
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* of the number of words in DCache line
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*/
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dcl_size = CTR_DLINE_SIZE(ctr);
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/* Size of word shifted by cache line size */
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return (sizeof(int) << dcl_size);
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}
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void
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cpu_flush_dcache(const void *ptr, size_t len)
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{
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uint64_t cl_size;
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vm_offset_t addr, end;
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cl_size = get_dcache_line_size();
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/* Calculate end address to clean */
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end = (vm_offset_t)ptr + (vm_offset_t)len;
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/* Align start address to cache line */
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addr = (vm_offset_t)ptr;
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addr = rounddown2(addr, cl_size);
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for (; addr < end; addr += cl_size)
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__asm __volatile("dc civac, %0" : : "r" (addr) : "memory");
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/* Full system DSB */
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__asm __volatile("dsb sy" : : : "memory");
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}
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void
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cpu_inval_icache(const void *ptr, size_t len)
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{
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/* NULL ptr or 0 len means all */
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if (ptr == NULL || len == 0) {
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__asm __volatile(
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"ic ialluis \n"
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"dsb ish \n"
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: : : "memory");
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return;
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}
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/* TODO: Other cache ranges if necessary */
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}
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