dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
185 lines
6.8 KiB
C
185 lines
6.8 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-iob1-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon iob1.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_IOB1_DEFS_H__
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#define __CVMX_IOB1_DEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_IOB1_BIST_STATUS CVMX_IOB1_BIST_STATUS_FUNC()
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static inline uint64_t CVMX_IOB1_BIST_STATUS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_IOB1_BIST_STATUS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011800F00107F8ull);
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}
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#else
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#define CVMX_IOB1_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00107F8ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_IOB1_CTL_STATUS CVMX_IOB1_CTL_STATUS_FUNC()
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static inline uint64_t CVMX_IOB1_CTL_STATUS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_IOB1_CTL_STATUS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011800F0010050ull);
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}
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#else
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#define CVMX_IOB1_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0010050ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_IOB1_TO_CMB_CREDITS CVMX_IOB1_TO_CMB_CREDITS_FUNC()
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static inline uint64_t CVMX_IOB1_TO_CMB_CREDITS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_IOB1_TO_CMB_CREDITS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011800F00100B0ull);
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}
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#else
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#define CVMX_IOB1_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00100B0ull))
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#endif
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/**
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* cvmx_iob1_bist_status
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*
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* IOB_BIST_STATUS = BIST Status of IOB Memories
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*
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* The result of the BIST run on the IOB memories.
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*/
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union cvmx_iob1_bist_status {
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uint64_t u64;
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struct cvmx_iob1_bist_status_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_9_63 : 55;
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uint64_t xmdfif : 1; /**< xmdfif_bist_status */
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uint64_t xmcfif : 1; /**< xmcfif_bist_status */
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uint64_t iorfif : 1; /**< iorfif_bist_status */
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uint64_t rsdfif : 1; /**< rsdfif_bist_status */
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uint64_t iocfif : 1; /**< iocfif_bist_status */
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uint64_t reserved_2_3 : 2;
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uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */
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uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */
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#else
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uint64_t icrp1 : 1;
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uint64_t icrp0 : 1;
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uint64_t reserved_2_3 : 2;
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uint64_t iocfif : 1;
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uint64_t rsdfif : 1;
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uint64_t iorfif : 1;
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uint64_t xmcfif : 1;
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uint64_t xmdfif : 1;
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uint64_t reserved_9_63 : 55;
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#endif
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} s;
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struct cvmx_iob1_bist_status_s cn68xx;
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struct cvmx_iob1_bist_status_s cn68xxp1;
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};
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typedef union cvmx_iob1_bist_status cvmx_iob1_bist_status_t;
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/**
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* cvmx_iob1_ctl_status
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*
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* IOB Control Status = IOB Control and Status Register
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*
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* Provides control for IOB functions.
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*/
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union cvmx_iob1_ctl_status {
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uint64_t u64;
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struct cvmx_iob1_ctl_status_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63 : 53;
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uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio
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is greater then 3:1. Writes should be followed by an
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immediate read. */
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uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */
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uint64_t reserved_0_5 : 6;
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#else
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uint64_t reserved_0_5 : 6;
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uint64_t xmc_per : 4;
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uint64_t fif_dly : 1;
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uint64_t reserved_11_63 : 53;
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#endif
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} s;
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struct cvmx_iob1_ctl_status_s cn68xx;
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struct cvmx_iob1_ctl_status_s cn68xxp1;
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};
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typedef union cvmx_iob1_ctl_status cvmx_iob1_ctl_status_t;
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/**
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* cvmx_iob1_to_cmb_credits
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*
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* IOB_TO_CMB_CREDITS = IOB To CMB Credits
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*
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* Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
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*/
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union cvmx_iob1_to_cmb_credits {
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uint64_t u64;
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struct cvmx_iob1_to_cmb_credits_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_10_63 : 54;
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uint64_t pko_rd : 4; /**< Number of PKO reads that can be out to L2C where
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0 == 16-credits. */
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uint64_t reserved_3_5 : 3;
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uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C
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where 0 == 8-credits. */
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#else
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uint64_t ncb_wr : 3;
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uint64_t reserved_3_5 : 3;
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uint64_t pko_rd : 4;
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uint64_t reserved_10_63 : 54;
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#endif
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} s;
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struct cvmx_iob1_to_cmb_credits_s cn68xx;
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struct cvmx_iob1_to_cmb_credits_s cn68xxp1;
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};
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typedef union cvmx_iob1_to_cmb_credits cvmx_iob1_to_cmb_credits_t;
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#endif
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