e8ce55117b
rather than forwarding interrupts from the clock devices around using IPIs: - Add an IDT vector that pushes a clock frame and calls lapic_handle_timer(). - Add functions to program the local APIC timer including setting the divisor, and setting up the timer to either down a periodic countdown or one-shot countdown. - Add a lapic_setup_clock() function that the BSP calls from cpu_init_clocks() to setup the local APIC timer if it is going to be used. The setup uses a one-shot countdown to calibrate the timer. We then program the timer on each CPU to fire at a frequency of hz * 3. stathz is defined as freq / 23 (hz * 3 / 23), and profhz is defined as freq / 2 (hz * 3 / 2). This gives the clocks relatively prime divisors while keeping a low LCM for the frequency of the clock interrupts. Thanks to Peter Jeremy for suggesting this approach. - Remove the hardclock and statclock forwarding code including the two associated IPIs. The bitmap IPI handler has now effectively degenerated to just IPI_AST. - When the local APIC timer is used we don't turn the RTC on at all, but we still enable interrupts on the ISA timer 0 (i8254) for timecounting purposes.
384 lines
8.7 KiB
ArmAsm
384 lines
8.7 KiB
ArmAsm
/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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/*
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* Interrupt entry points for external interrupts triggered by I/O APICs
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* as well as IPI handlers.
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*/
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#include <machine/asmacros.h>
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#include <machine/apicreg.h>
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#include <machine/smptests.h>
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#include "assym.s"
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/*
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* Macros to create and destroy a trap frame.
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*/
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; /* 8 ints */ \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es ; \
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pushl %fs
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#define POP_FRAME \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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/*
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* I/O Interrupt Entry Point. Rather than having one entry point for
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* each interrupt source, we use one entry point for each 32-bit word
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* in the ISR. The handler determines the highest bit set in the ISR,
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* translates that into a vector, and passes the vector to the
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* lapic_handle_intr() function.
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*/
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#define ISR_VEC(index, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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movl %eax, %ds ; \
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movl %eax, %es ; \
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movl $KPSEL, %eax ; /* reload with per-CPU data segment */ \
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movl %eax, %fs ; \
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FAKE_MCOUNT(TF_EIP(%esp)) ; \
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movl lapic, %edx ; /* pointer to local APIC */ \
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movl LA_ISR + 16 * (index)(%edx), %eax ; /* load ISR */ \
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bsrl %eax, %eax ; /* index of highset set bit in ISR */ \
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jz 2f ; \
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addl $(32 * index),%eax ; \
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1: ; \
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pushl %eax ; /* pass the IRQ */ \
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call lapic_handle_intr ; \
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addl $4, %esp ; /* discard parameter */ \
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MEXITCOUNT ; \
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jmp doreti ; \
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2: movl $-1, %eax ; /* send a vector of -1 */ \
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jmp 1b
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(spuriousint)
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/* No EOI cycle used here */
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iret
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ISR_VEC(1, apic_isr1)
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ISR_VEC(2, apic_isr2)
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ISR_VEC(3, apic_isr3)
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ISR_VEC(4, apic_isr4)
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ISR_VEC(5, apic_isr5)
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ISR_VEC(6, apic_isr6)
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ISR_VEC(7, apic_isr7)
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/*
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* Local APIC periodic timer handler.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(timerint)
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PUSH_FRAME
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movl $KDSEL, %eax /* reload with kernel's data segment */
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movl %eax, %ds
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movl %eax, %es
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movl $KPSEL, %eax
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movl %eax, %fs
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movl lapic, %edx
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movl $0, LA_EOI(%edx) /* End Of Interrupt to APIC */
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FAKE_MCOUNT(TF_EIP(%esp))
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pushl $0 /* XXX convert trapframe to clockframe */
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call lapic_handle_timer
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addl $4, %esp /* XXX convert clockframe to trapframe */
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MEXITCOUNT
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jmp doreti
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#ifdef SMP
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/*
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* Global address space TLB shootdown.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invltlb)
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pushl %eax
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pushl %ds
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movl $KDSEL, %eax /* Kernel data selector */
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movl %eax, %ds
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax /* Private space selector */
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movl %eax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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incl xhits_gbl(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl %cr3, %eax /* invalidate the TLB */
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movl %eax, %cr3
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movl lapic, %eax
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movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popl %ds
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popl %eax
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iret
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/*
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* Single page TLB shootdown
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invlpg)
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pushl %eax
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pushl %ds
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movl $KDSEL, %eax /* Kernel data selector */
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movl %eax, %ds
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax /* Private space selector */
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movl %eax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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incl xhits_pg(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl smp_tlb_addr1, %eax
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invlpg (%eax) /* invalidate single page */
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movl lapic, %eax
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movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popl %ds
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popl %eax
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iret
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/*
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* Page range TLB shootdown.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invlrng)
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pushl %eax
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pushl %edx
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pushl %ds
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movl $KDSEL, %eax /* Kernel data selector */
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movl %eax, %ds
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax /* Private space selector */
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movl %eax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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incl xhits_rng(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl smp_tlb_addr1, %edx
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movl smp_tlb_addr2, %eax
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1: invlpg (%edx) /* invalidate single page */
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addl $PAGE_SIZE, %edx
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cmpl %eax, %edx
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jb 1b
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movl lapic, %eax
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movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popl %ds
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popl %edx
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popl %eax
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iret
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/*
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* Forward hardclock to another CPU. Pushes a clockframe and calls
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* forwarded_hardclock().
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(ipi_intr_bitmap_handler)
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PUSH_FRAME
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movl $KDSEL, %eax /* reload with kernel's data segment */
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movl %eax, %ds
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movl %eax, %es
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movl $KPSEL, %eax
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movl %eax, %fs
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movl lapic, %edx
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movl $0, LA_EOI(%edx) /* End Of Interrupt to APIC */
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FAKE_MCOUNT(TF_EIP(%esp))
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pushl $0 /* XXX convert trapframe to clockframe */
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call ipi_bitmap_handler
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addl $4, %esp /* XXX convert clockframe to trapframe */
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MEXITCOUNT
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jmp doreti
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/*
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* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
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*
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* - Signals its receipt.
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* - Waits for permission to restart.
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* - Signals its restart.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(cpustop)
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pushl %ebp
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movl %esp, %ebp
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %ds /* save current data segment */
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pushl %es
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pushl %fs
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movl $KDSEL, %eax
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movl %eax, %ds /* use KERNEL data segment */
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movl %eax, %es
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movl $KPSEL, %eax
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movl %eax, %fs
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movl lapic, %eax
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movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
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movl PCPU(CPUID), %eax
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imull $PCB_SIZE, %eax
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leal CNAME(stoppcbs)(%eax), %eax
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pushl %eax
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call CNAME(savectx) /* Save process context */
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addl $4, %esp
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movl PCPU(CPUID), %eax
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lock
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btsl %eax, CNAME(stopped_cpus) /* stopped_cpus |= (1<<id) */
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1:
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btl %eax, CNAME(started_cpus) /* while (!(started_cpus & (1<<id))) */
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jnc 1b
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lock
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btrl %eax, CNAME(started_cpus) /* started_cpus &= ~(1<<id) */
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lock
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btrl %eax, CNAME(stopped_cpus) /* stopped_cpus &= ~(1<<id) */
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test %eax, %eax
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jnz 2f
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movl CNAME(cpustop_restartfunc), %eax
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test %eax, %eax
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jz 2f
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movl $0, CNAME(cpustop_restartfunc) /* One-shot */
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call *%eax
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2:
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popl %fs
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popl %es
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popl %ds /* restore previous data segment */
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popl %edx
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popl %ecx
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popl %eax
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movl %ebp, %esp
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popl %ebp
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iret
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/*
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* Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
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*
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* - Calls the generic rendezvous action function.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(rendezvous)
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PUSH_FRAME
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movl $KDSEL, %eax
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movl %eax, %ds /* use KERNEL data segment */
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movl %eax, %es
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movl $KPSEL, %eax
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movl %eax, %fs
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call smp_rendezvous_action
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movl lapic, %eax
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movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
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POP_FRAME
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iret
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/*
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* Clean up when we lose out on the lazy context switch optimization.
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* ie: when we are about to release a PTD but a cpu is still borrowing it.
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*/
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SUPERALIGN_TEXT
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IDTVEC(lazypmap)
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PUSH_FRAME
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movl $KDSEL, %eax
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movl %eax, %ds /* use KERNEL data segment */
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movl %eax, %es
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movl $KPSEL, %eax
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movl %eax, %fs
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call pmap_lazyfix_action
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movl lapic, %eax
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movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
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POP_FRAME
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iret
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#endif /* SMP */
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