04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
332 lines
9.2 KiB
C
332 lines
9.2 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the Thunder specific devices
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*
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* <hr>$Revision: 49448 $<hr>
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*
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*/
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#include "cvmx.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-thunder.h"
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#include "cvmx-gpio.h"
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#include "cvmx-twsi.h"
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static const int BYPASS_STATUS = 1<<5; /* GPIO 5 */
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static const int BYPASS_EN = 1<<6; /* GPIO 6 */
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static const int WDT_BP_CLR = 1<<7; /* GPIO 7 */
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static const int RTC_CTL_ADDR = 0x7;
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static const int RTC_CTL_BIT_EOSC = 0x80;
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static const int RTC_CTL_BIT_WACE = 0x40;
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static const int RTC_CTL_BIT_WD_ALM = 0x20;
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static const int RTC_CTL_BIT_WDSTR = 0x8;
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static const int RTC_CTL_BIT_AIE = 0x1;
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static const int RTC_WD_ALM_CNT_BYTE0_ADDR = 0x4;
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#define CVMX_LAN_BYPASS_MSG(...) do {} while(0)
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/*
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* Board-specifc RTC read
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* Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
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*/
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uint32_t cvmx_rtc_ds1374_read(void)
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{
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int retry;
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uint8_t sec;
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uint32_t time;
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for(retry=0; retry<2; retry++)
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{
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time = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0);
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time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 8;
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time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 16;
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time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 24;
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sec = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0);
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if (sec == (time & 0xff))
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break; /* Time did not roll-over, value is correct */
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}
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return time;
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}
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/*
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* Board-specific RTC write
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* Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
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*/
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int cvmx_rtc_ds1374_write(uint32_t time)
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{
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int rc;
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int retry;
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uint8_t sec;
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for(retry=0; retry<2; retry++)
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{
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rc = cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x0, time & 0xff);
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rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x1, (time >> 8) & 0xff);
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rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x2, (time >> 16) & 0xff);
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rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x3, (time >> 24) & 0xff);
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sec = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0);
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if (sec == (time & 0xff))
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break; /* Time did not roll-over, value is correct */
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}
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return (rc ? -1 : 0);
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}
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static int cvmx_rtc_ds1374_alarm_config(int WD, int WDSTR, int AIE)
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{
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int val;
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val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR);
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val = val & ~RTC_CTL_BIT_EOSC; /* Make sure that oscillator is running */
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WD?(val = val | RTC_CTL_BIT_WD_ALM):(val = val & ~RTC_CTL_BIT_WD_ALM);
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WDSTR?(val = val | RTC_CTL_BIT_WDSTR):(val = val & ~RTC_CTL_BIT_WDSTR);
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AIE?(val = val | RTC_CTL_BIT_AIE):(val = val & ~RTC_CTL_BIT_AIE);
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cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val);
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return 0;
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}
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static int cvmx_rtc_ds1374_alarm_set(int alarm_on)
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{
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uint8_t val;
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if (alarm_on)
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{
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val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR);
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cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val | RTC_CTL_BIT_WACE);
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}
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else
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{
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val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR);
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cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val & ~RTC_CTL_BIT_WACE);
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}
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return 0;
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}
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static int cvmx_rtc_ds1374_alarm_counter_set(uint32_t interval)
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{
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int i;
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int rc = 0;
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for(i=0;i<3;i++)
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{
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rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, RTC_WD_ALM_CNT_BYTE0_ADDR+i, interval & 0xFF);
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interval >>= 8;
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}
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return rc;
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}
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#if 0 /* XXX unused */
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static uint32_t cvmx_rtc_ds1374_alarm_counter_get(void)
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{
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int i;
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uint32_t interval = 0;
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for(i=0;i<3;i++)
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{
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interval |= ( cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_WD_ALM_CNT_BYTE0_ADDR+i) & 0xff) << (i*8);
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}
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return interval;
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}
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#endif
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#ifdef CVMX_RTC_DEBUG
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void cvmx_rtc_ds1374_dump_state(void)
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{
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int i = 0;
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cvmx_dprintf("RTC:\n");
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cvmx_dprintf("%d : %02X ", i, cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0));
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for(i=1; i<10; i++)
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{
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cvmx_dprintf("%02X ", cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR));
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}
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cvmx_dprintf("\n");
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}
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#endif /* CVMX_RTC_DEBUG */
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/*
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* LAN bypass functionality
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*/
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/* Private initialization function */
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static int cvmx_lan_bypass_init(void)
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{
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const int CLR_PULSE = 100; /* Longer than 100 ns (on CPUs up to 1 GHz) */
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//Clear GPIO 6
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cvmx_gpio_clear(BYPASS_EN);
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//Disable WDT
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cvmx_rtc_ds1374_alarm_set(0);
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//GPIO(7) Send a low pulse
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cvmx_gpio_clear(WDT_BP_CLR);
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cvmx_wait(CLR_PULSE);
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cvmx_gpio_set(WDT_BP_CLR);
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return 0;
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}
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/**
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* Set LAN bypass mode.
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*
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* Supported modes are:
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* - CVMX_LAN_BYPASS_OFF
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* <br>LAN ports are connected ( port 0 <--> Octeon <--> port 1 )
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*
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* - CVMX_LAN_BYPASS_GPIO
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* <br>LAN bypass is controlled by software using cvmx_lan_bypass_force() function.
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* When transitioning to this mode, default is LAN bypass enabled
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* ( port 0 <--> port 1, -- Octeon ).
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*
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* - CVMX_LAN_BYPASS_WATCHDOG
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* <br>LAN bypass is inactive as long as a watchdog is kept alive.
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* The default expiration time is 1 second and the function to
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* call periodically to prevent watchdog expiration is
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* cvmx_lan_bypass_keep_alive().
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*
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* @param mode LAN bypass mode
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*
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* @return Error code, or 0 in case of success
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*/
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int cvmx_lan_bypass_mode_set(cvmx_lan_bypass_mode_t mode)
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{
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switch(mode)
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{
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case CVMX_LAN_BYPASS_GPIO:
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/* make lan bypass enable */
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cvmx_lan_bypass_init();
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cvmx_gpio_set(BYPASS_EN);
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CVMX_LAN_BYPASS_MSG("Enable LAN bypass by GPIO. \n");
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break;
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case CVMX_LAN_BYPASS_WATCHDOG:
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/* make lan bypass enable */
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cvmx_lan_bypass_init();
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/* Set WDT parameters and turn it on */
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cvmx_rtc_ds1374_alarm_counter_set(0x1000); /* 4096 ticks = 1 sec */
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cvmx_rtc_ds1374_alarm_config(1,1,1);
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cvmx_rtc_ds1374_alarm_set(1);
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CVMX_LAN_BYPASS_MSG("Enable LAN bypass by WDT. \n");
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break;
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case CVMX_LAN_BYPASS_OFF:
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/* make lan bypass disable */
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cvmx_lan_bypass_init();
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CVMX_LAN_BYPASS_MSG("Disable LAN bypass. \n");
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break;
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default:
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CVMX_LAN_BYPASS_MSG("%s: LAN bypass mode %d not supported\n", __FUNCTION__, mode);
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break;
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}
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return 0;
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}
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/**
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* Refresh watchdog timer.
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*
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* Call periodically (less than 1 second) to prevent triggering LAN bypass.
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* The alternative cvmx_lan_bypass_keep_alive_ms() is provided for cases
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* where a variable interval is required.
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*/
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void cvmx_lan_bypass_keep_alive(void)
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{
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cvmx_rtc_ds1374_alarm_counter_set(0x1000); /* 4096 ticks = 1 second */
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}
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/**
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* Refresh watchdog timer, setting a specific expiration interval.
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*
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* @param interval_ms Interval, in milliseconds, to next watchdog expiration.
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*/
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void cvmx_lan_bypass_keep_alive_ms(uint32_t interval_ms)
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{
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cvmx_rtc_ds1374_alarm_counter_set((interval_ms * 0x1000) / 1000);
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}
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/**
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* Control LAN bypass via software.
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*
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* @param force_bypass Force LAN bypass to active (1) or inactive (0)
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*
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* @return Error code, or 0 in case of success
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*/
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int cvmx_lan_bypass_force(int force_bypass)
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{
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if (force_bypass)
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{
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//Set GPIO 6
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cvmx_gpio_set(BYPASS_EN);
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}
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else
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{
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cvmx_lan_bypass_init();
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}
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return 0;
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}
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/**
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* Return status of LAN bypass circuit.
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*
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* @return 1 if ports are in LAN bypass, or 0 if normally connected
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*/
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int cvmx_lan_bypass_is_active(void)
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{
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return !!(cvmx_gpio_read() & BYPASS_STATUS);
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}
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