164 lines
5.5 KiB
C
164 lines
5.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de>
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* Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <machine/platform.h>
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#include <machine/platformvar.h>
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#include <arm/freescale/imx/imx6_machdep.h>
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#define SCU_PHYSBASE 0x00a00000
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#define SCU_SIZE 0x00001000
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#define SCU_CONTROL_REG 0x00
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#define SCU_CONTROL_ENABLE (1 << 0)
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#define SCU_CONFIG_REG 0x04
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#define SCU_CONFIG_REG_NCPU_MASK 0x03
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#define SCU_CPUPOWER_REG 0x08
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#define SCU_INV_TAGS_REG 0x0c
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#define SCU_DIAG_CONTROL 0x30
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#define SCU_DIAG_DISABLE_MIGBIT (1 << 0)
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#define SCU_FILTER_START_REG 0x40
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#define SCU_FILTER_END_REG 0x44
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#define SCU_SECURE_ACCESS_REG 0x50
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#define SCU_NONSECURE_ACCESS_REG 0x54
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#define SRC_PHYSBASE 0x020d8000
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#define SRC_SIZE 0x4000
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#define SRC_CONTROL_REG 0x00
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#define SRC_CONTROL_C1ENA_SHIFT 22 /* Bit for Core 1 enable */
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#define SRC_CONTROL_C1RST_SHIFT 14 /* Bit for Core 1 reset */
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#define SRC_GPR0_C1FUNC 0x20 /* Register for Core 1 entry func */
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#define SRC_GPR1_C1ARG 0x24 /* Register for Core 1 entry arg */
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void
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imx6_mp_setmaxid(platform_t plat)
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{
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bus_space_handle_t scu;
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int hwcpu, ncpu;
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uint32_t val;
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/* If we've already set the global vars don't bother to do it again. */
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if (mp_ncpus != 0)
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return;
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
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panic("Couldn't map the SCU\n");
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val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
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hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1;
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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ncpu = hwcpu;
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TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
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if (ncpu < 1 || ncpu > hwcpu)
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ncpu = hwcpu;
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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void
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imx6_mp_start_ap(platform_t plat)
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{
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bus_space_handle_t scu;
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bus_space_handle_t src;
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uint32_t val;
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int i;
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
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panic("Couldn't map the SCU\n");
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if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
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panic("Couldn't map the system reset controller (SRC)\n");
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/*
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* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
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* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
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* the bits for cores that are not present.
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*/
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
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/*
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* Erratum ARM/MP: 764369 (problems with cache maintenance).
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* Setting the "disable-migratory bit" in the undocumented SCU
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* Diagnostic Control Register helps work around the problem.
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*/
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val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
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val | SCU_DIAG_DISABLE_MIGBIT);
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/*
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* Enable the SCU, then clean the cache on this core. After these two
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* operations the cache tag ram in the SCU is coherent with the contents
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* of the cache on this core. The other cores aren't running yet so
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* their caches can't contain valid data yet, but we've initialized
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* their SCU tag ram above, so they will be coherent from startup.
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*/
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val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
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val | SCU_CONTROL_ENABLE);
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dcache_wbinv_poc_all();
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/*
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* For each AP core, set the entry point address and argument registers,
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* and set the core-enable and core-reset bits in the control register.
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*/
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val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
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for (i=1; i < mp_ncpus; i++) {
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bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
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pmap_kextract((vm_offset_t)mpentry));
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bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0);
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val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
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( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
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}
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bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
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}
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