c5f8f8946c
support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
203 lines
6.1 KiB
C
203 lines
6.1 KiB
C
/* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */
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/*-
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _MACHINE_CPUCONF_H_
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#define _MACHINE_CPUCONF_H_
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/*
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* IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
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* "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
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* YOU ARE ADDING SUPPORT FOR.
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*/
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/*
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* Step 1: Count the number of CPU types configured into the kernel.
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*/
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#define CPU_NTYPES (defined(CPU_ARM7TDMI) + \
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defined(CPU_ARM8) + defined(CPU_ARM9) + \
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defined(CPU_ARM9E) + \
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defined(CPU_ARM10) + \
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defined(CPU_ARM1136) + \
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defined(CPU_ARM1176) + \
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defined(CPU_SA110) + defined(CPU_SA1100) + \
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defined(CPU_SA1110) + \
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defined(CPU_IXP12X0) + \
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defined(CPU_XSCALE_80200) + \
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defined(CPU_XSCALE_80321) + \
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defined(CPU_XSCALE_PXA2X0) + \
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defined(CPU_FA526) + \
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defined(CPU_FA626TE) + \
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defined(CPU_XSCALE_IXP425)) + \
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defined(CPU_CORTEXA) + \
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defined(CPU_MV_PJ4B)
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/*
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* Step 2: Determine which ARM architecture versions are configured.
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*/
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#if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
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defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
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defined(CPU_IXP12X0) || defined(CPU_FA526))
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#define ARM_ARCH_4 1
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#else
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#define ARM_ARCH_4 0
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#endif
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#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
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defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_FA626TE))
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#define ARM_ARCH_5 1
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#else
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#define ARM_ARCH_5 0
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#endif
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#if !defined(ARM_ARCH_6)
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B)
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#define ARM_ARCH_6 1
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#else
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#define ARM_ARCH_6 0
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#endif
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#endif
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#if defined(CPU_CORTEXA)
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#define ARM_ARCH_7A 1
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#else
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#define ARM_ARCH_7A 0
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#endif
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#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A)
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#if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
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#error ARM_NARCH is 0
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#endif
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#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A
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/*
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* We could support Thumb code on v4T, but the lack of clean interworking
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* makes that hard.
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*/
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#define THUMB_CODE
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#endif
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/*
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* Step 3: Define which MMU classes are configured:
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*
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* ARM_MMU_MEMC Prehistoric, external memory controller
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* and MMU for ARMv2 CPUs.
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*
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* ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
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*
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* ARM_MMU_V6 ARMv6 MMU.
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*
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* ARM_MMU_V7 ARMv7 MMU.
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*
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* ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
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* ARM MMU, but has no write-through cache mode.
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*
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* ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
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* MMU, but also has several extensions which
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* require different PTE layout to use.
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*/
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#if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
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#define ARM_MMU_MEMC 1
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#else
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#define ARM_MMU_MEMC 0
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#endif
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#if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
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defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \
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defined(CPU_ARM10) || defined(CPU_FA526) || \
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defined(CPU_FA626TE))
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#define ARM_MMU_GENERIC 1
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#else
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#define ARM_MMU_GENERIC 0
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#endif
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B)
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#define ARM_MMU_V6 1
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#else
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#define ARM_MMU_V6 0
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#endif
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#if defined(CPU_CORTEXA)
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#define ARM_MMU_V7 1
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#else
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#define ARM_MMU_V7 0
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#endif
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#if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
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defined(CPU_IXP12X0))
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#define ARM_MMU_SA1 1
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#else
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#define ARM_MMU_SA1 0
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#endif
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#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
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#define ARM_MMU_XSCALE 1
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#else
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#define ARM_MMU_XSCALE 0
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#endif
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#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_V6 + \
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ARM_MMU_V7 + ARM_MMU_SA1 + ARM_MMU_XSCALE)
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#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
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#error ARM_NMMUS is 0
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#endif
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/*
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* Step 4: Define features that may be present on a subset of CPUs
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*
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* ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
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*/
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#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
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#define ARM_XSCALE_PMU 1
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#else
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#define ARM_XSCALE_PMU 0
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#endif
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#if defined(CPU_XSCALE_81342)
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#define CPU_XSCALE_CORE3
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#endif
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#endif /* _MACHINE_CPUCONF_H_ */
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