325 lines
10 KiB
C
325 lines
10 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _PCIVAR_H_
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#define _PCIVAR_H_
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#include <sys/queue.h>
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/* some PCI bus constants */
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#define PCI_BUSMAX 255 /* highest supported bus number */
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#define PCI_SLOTMAX 31 /* highest supported slot number */
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#define PCI_FUNCMAX 7 /* highest supported function number */
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#define PCI_REGMAX 255 /* highest supported config register addr. */
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#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
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#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
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#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
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/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
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#ifdef PCI_A64
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typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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#else
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typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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#endif
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/* config header information common to all header types */
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typedef struct pcicfg {
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struct device *dev; /* device which owns this */
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u_int16_t subvendor; /* card vendor ID */
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u_int16_t subdevice; /* card device ID, assigned by card vendor */
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u_int16_t vendor; /* chip vendor ID */
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u_int16_t device; /* chip device ID, assigned by chip vendor */
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u_int16_t cmdreg; /* disable/enable chip and PCI options */
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u_int16_t statreg; /* supported PCI features and error state */
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u_int8_t baseclass; /* chip PCI class */
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u_int8_t subclass; /* chip PCI subclass */
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u_int8_t progif; /* chip PCI programming interface */
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u_int8_t revid; /* chip revision ID */
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u_int8_t hdrtype; /* chip config header type */
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u_int8_t cachelnsz; /* cache line size in 4byte units */
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u_int8_t intpin; /* PCI interrupt pin */
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u_int8_t intline; /* interrupt line (IRQ for PC arch) */
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u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
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u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
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u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
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u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
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u_int8_t nummaps; /* actual number of PCI maps used */
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u_int8_t bus; /* config space bus address */
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u_int8_t slot; /* config space slot address */
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u_int8_t func; /* config space function number */
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u_int16_t pp_cap; /* PCI power management capabilities */
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u_int8_t pp_status; /* config space address of PCI power status reg */
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u_int8_t pp_pmcsr; /* config space address of PMCSR reg */
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u_int8_t pp_data; /* config space address of PCI power data reg */
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} pcicfgregs;
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/* additional type 1 device config header information (PCI to PCI bridge) */
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#ifdef PCI_A64
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#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
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#else
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#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
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#endif /* PCI_A64 */
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#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
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#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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typedef struct {
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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u_int32_t membase; /* base address of memory window */
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u_int32_t memlimit; /* topmost address of memory window */
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u_int32_t iobase; /* base address of port window */
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u_int32_t iolimit; /* topmost address of port window */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* CardBus latency timer */
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} pcih1cfgregs;
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/* additional type 2 device config header information (CardBus bridge) */
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typedef struct {
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u_int32_t membase0; /* base address of memory window */
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u_int32_t memlimit0; /* topmost address of memory window */
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u_int32_t membase1; /* base address of memory window */
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u_int32_t memlimit1; /* topmost address of memory window */
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u_int32_t iobase0; /* base address of port window */
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u_int32_t iolimit0; /* topmost address of port window */
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u_int32_t iobase1; /* base address of port window */
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u_int32_t iolimit1; /* topmost address of port window */
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u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* CardBus latency timer */
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} pcih2cfgregs;
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extern u_int32_t pci_numdevs;
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/* Only if the prerequisites are present */
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#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
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struct pci_devinfo {
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STAILQ_ENTRY(pci_devinfo) pci_links;
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struct resource_list resources;
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pcicfgregs cfg;
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struct pci_conf conf;
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};
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#endif
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#ifdef __alpha__
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vm_offset_t pci_cvt_to_dense (vm_offset_t);
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vm_offset_t pci_cvt_to_bwx (vm_offset_t);
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#endif /* __alpha__ */
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#ifdef _SYS_BUS_H_
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#include "pci_if.h"
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/*
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* Define pci-specific resource flags for accessing memory via dense
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* or bwx memory spaces. These flags are ignored on i386.
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*/
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#define PCI_RF_DENSE 0x10000
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#define PCI_RF_BWX 0x20000
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enum pci_device_ivars {
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PCI_IVAR_SUBVENDOR,
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PCI_IVAR_SUBDEVICE,
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PCI_IVAR_VENDOR,
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PCI_IVAR_DEVICE,
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PCI_IVAR_DEVID,
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PCI_IVAR_CLASS,
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PCI_IVAR_SUBCLASS,
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PCI_IVAR_PROGIF,
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PCI_IVAR_REVID,
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PCI_IVAR_INTPIN,
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PCI_IVAR_IRQ,
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PCI_IVAR_BUS,
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PCI_IVAR_SLOT,
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PCI_IVAR_FUNCTION,
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};
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/*
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* Simplified accessors for pci devices
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*/
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#define PCI_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(pci, var, PCI, ivar, type)
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PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
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PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
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PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
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PCI_ACCESSOR(device, DEVICE, u_int16_t)
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PCI_ACCESSOR(devid, DEVID, u_int32_t)
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PCI_ACCESSOR(class, CLASS, u_int8_t)
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PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
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PCI_ACCESSOR(progif, PROGIF, u_int8_t)
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PCI_ACCESSOR(revid, REVID, u_int8_t)
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PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
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PCI_ACCESSOR(irq, IRQ, u_int8_t)
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PCI_ACCESSOR(bus, BUS, u_int8_t)
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PCI_ACCESSOR(slot, SLOT, u_int8_t)
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PCI_ACCESSOR(function, FUNCTION, u_int8_t)
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#undef PCI_ACCESSOR
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/*
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* Operations on configuration space.
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*/
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static __inline u_int32_t
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pci_read_config(device_t dev, int reg, int width)
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{
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return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
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}
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static __inline void
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pci_write_config(device_t dev, int reg, u_int32_t val, int width)
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{
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PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
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}
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/*
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* Ivars for pci bridges.
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*/
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/*typedef enum pci_device_ivars pcib_device_ivars;*/
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enum pcib_device_ivars {
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PCIB_IVAR_BUS
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};
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#define PCIB_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
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PCIB_ACCESSOR(bus, BUS, u_int32_t)
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#undef PCIB_ACCESSOR
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/*
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* PCI interrupt validation. Invalid interrupt values such as 0 or 128
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* on i386 or other platforms should be mapped out in the MD pcireadconf
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* code and not here, since the only MI invalid IRQ is 255.
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*/
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#define PCI_INVALID_IRQ 255
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#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
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/*
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* Convenience functions.
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*
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* These should be used in preference to manually manipulating
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* configuration space.
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*/
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static __inline void
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pci_enable_busmaster(device_t dev)
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{
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PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev);
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}
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static __inline void
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pci_disable_busmaster(device_t dev)
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{
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PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev);
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}
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static __inline void
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pci_enable_io(device_t dev, int space)
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{
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PCI_ENABLE_IO(device_get_parent(dev), dev, space);
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}
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static __inline void
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pci_disable_io(device_t dev, int space)
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{
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PCI_DISABLE_IO(device_get_parent(dev), dev, space);
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}
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/*
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* PCI power states are as defined by ACPI:
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*
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* D0 State in which device is on and running. It is receiving full
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* power from the system and delivering full functionality to the user.
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* D1 Class-specific low-power state in which device context may or may not
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* be lost. Buses in D1 cannot do anything to the bus that would force
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* devices on that bus to loose context.
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* D2 Class-specific low-power state in which device context may or may
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* not be lost. Attains greater power savings than D1. Buses in D2
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* can cause devices on that bus to loose some context. Devices in D2
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* must be prepared for the bus to be in D2 or higher.
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* D3 State in which the device is off and not running. Device context is
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* lost. Power can be removed from the device.
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*/
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#define PCI_POWERSTATE_D0 0
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#define PCI_POWERSTATE_D1 1
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#define PCI_POWERSTATE_D2 2
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#define PCI_POWERSTATE_D3 3
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#define PCI_POWERSTATE_UNKNOWN -1
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static __inline int
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pci_set_powerstate(device_t dev, int state)
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{
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return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
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}
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static __inline int
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pci_get_powerstate(device_t dev)
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{
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return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
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}
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device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
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device_t pci_find_device(u_int16_t, u_int16_t);
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#endif /* _SYS_BUS_H_ */
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/*
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* cdev switch for control device, initialised in generic PCI code
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*/
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extern struct cdevsw pcicdev;
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/*
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* List of all PCI devices, generation count for the list.
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*/
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STAILQ_HEAD(devlist, pci_devinfo);
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extern struct devlist pci_devq;
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extern u_int32_t pci_generation;
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#endif /* _PCIVAR_H_ */
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