e829eb6d61
dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question. Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations. - Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class. - Move code common to Intel CPUs to file "hwpmc_intel.c". - Move TSC handling to file "hwpmc_tsc.c".
389 lines
8.9 KiB
C
389 lines
8.9 KiB
C
/*-
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* Copyright (c) 2008 Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <sys/systm.h>
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#include <machine/specialreg.h>
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/*
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* TSC support.
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*/
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#define TSC_CAPS PMC_CAP_READ
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struct tsc_descr {
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struct pmc_descr pm_descr; /* "base class" */
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};
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static struct tsc_descr tsc_pmcdesc[TSC_NPMCS] =
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{
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{
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.pm_descr =
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{
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.pd_name = "TSC",
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.pd_class = PMC_CLASS_TSC,
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.pd_caps = TSC_CAPS,
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.pd_width = 64
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}
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}
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};
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/*
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* Per-CPU data structure for TSCs.
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*/
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struct tsc_cpu {
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struct pmc_hw tc_hw;
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};
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static struct tsc_cpu **tsc_pcpu;
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static int
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tsc_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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(void) cpu;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < TSC_NPMCS,
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("[tsc,%d] illegal row index %d", __LINE__, ri));
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if (a->pm_class != PMC_CLASS_TSC)
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return (EINVAL);
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if ((pm->pm_caps & TSC_CAPS) == 0)
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return (EINVAL);
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if ((pm->pm_caps & ~TSC_CAPS) != 0)
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return (EPERM);
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if (a->pm_ev != PMC_EV_TSC_TSC ||
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a->pm_mode != PMC_MODE_SC)
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return (EINVAL);
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return (0);
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}
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static int
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tsc_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
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phw = &tsc_pcpu[cpu]->tc_hw;
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[tsc,%d] pm=%p phw->pm=%p hwpmc not unconfigured", __LINE__,
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pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return (0);
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}
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static int
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tsc_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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int error;
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size_t copied;
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const struct tsc_descr *pd;
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
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phw = &tsc_pcpu[cpu]->tc_hw;
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pd = &tsc_pmcdesc[ri];
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if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
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PMC_NAME_MAX, &copied)) != 0)
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return (error);
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pi->pm_class = pd->pm_descr.pd_class;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
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pi->pm_enabled = TRUE;
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*ppmc = phw->phw_pmc;
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} else {
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pi->pm_enabled = FALSE;
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*ppmc = NULL;
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}
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return (0);
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}
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static int
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tsc_get_config(int cpu, int ri, struct pmc **ppm)
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{
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(void) ri;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
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*ppm = tsc_pcpu[cpu]->tc_hw.phw_pmc;
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return (0);
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}
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static int
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tsc_get_msr(int ri, uint32_t *msr)
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{
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(void) ri;
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KASSERT(ri >= 0 && ri < TSC_NPMCS,
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("[tsc,%d] ri %d out of range", __LINE__, ri));
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*msr = MSR_TSC;
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return (0);
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}
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static int
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tsc_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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int ri;
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struct pmc_cpu *pc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal cpu %d", __LINE__, cpu));
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KASSERT(tsc_pcpu[cpu] != NULL, ("[tsc,%d] null pcpu", __LINE__));
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free(tsc_pcpu[cpu], M_PMC);
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tsc_pcpu[cpu] = NULL;
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ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC].pcd_ri;
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KASSERT(ri == 0 && ri < TSC_NPMCS, ("[tsc,%d] ri=%d", __LINE__,
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ri));
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pc = pmc_pcpu[cpu];
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pc->pc_hwpmcs[ri] = NULL;
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return (0);
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}
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static int
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tsc_pcpu_init(struct pmc_mdep *md, int cpu)
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{
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int ri;
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struct pmc_cpu *pc;
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struct tsc_cpu *tsc_pc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal cpu %d", __LINE__, cpu));
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KASSERT(tsc_pcpu, ("[tsc,%d] null pcpu", __LINE__));
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KASSERT(tsc_pcpu[cpu] == NULL, ("[tsc,%d] non-null per-cpu",
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__LINE__));
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tsc_pc = malloc(sizeof(struct tsc_cpu), M_PMC, M_WAITOK|M_ZERO);
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tsc_pc->tc_hw.phw_state = PMC_PHW_FLAG_IS_ENABLED |
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PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(0) |
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PMC_PHW_FLAG_IS_SHAREABLE;
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tsc_pcpu[cpu] = tsc_pc;
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ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC].pcd_ri;
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KASSERT(pmc_pcpu, ("[tsc,%d] null generic pcpu", __LINE__));
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pc = pmc_pcpu[cpu];
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KASSERT(pc, ("[tsc,%d] null generic per-cpu", __LINE__));
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pc->pc_hwpmcs[ri] = &tsc_pc->tc_hw;
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return (0);
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}
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static int
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tsc_read_pmc(int cpu, int ri, pmc_value_t *v)
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{
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struct pmc *pm;
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enum pmc_mode mode;
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const struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal ri %d", __LINE__, ri));
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phw = &tsc_pcpu[cpu]->tc_hw;
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pm = phw->phw_pmc;
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KASSERT(pm != NULL,
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("[tsc,%d] no owner for PHW [cpu%d,pmc%d]", __LINE__, cpu, ri));
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mode = PMC_TO_MODE(pm);
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KASSERT(mode == PMC_MODE_SC,
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("[tsc,%d] illegal pmc mode %d", __LINE__, mode));
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PMCDBG(MDP,REA,1,"tsc-read id=%d", ri);
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*v = rdtsc();
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return (0);
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}
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static int
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tsc_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw;
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(void) pmc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri == 0,
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("[tsc,%d] illegal row-index %d", __LINE__, ri));
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phw = &tsc_pcpu[cpu]->tc_hw;
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KASSERT(phw->phw_pmc == NULL,
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("[tsc,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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/*
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* Nothing to do.
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*/
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return (0);
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}
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static int
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tsc_start_pmc(int cpu, int ri)
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{
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(void) cpu;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
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return (0); /* TSCs are always running. */
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}
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static int
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tsc_stop_pmc(int cpu, int ri)
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{
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(void) cpu; (void) ri;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
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return (0); /* Cannot actually stop a TSC. */
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}
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static int
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tsc_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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(void) cpu; (void) ri; (void) v;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
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/*
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* The TSCs are used as timecounters by the kernel, so even
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* though some i386 CPUs support writeable TSCs, we don't
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* support writing changing TSC values through the HWPMC API.
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*/
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return (0);
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}
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int
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pmc_tsc_initialize(struct pmc_mdep *md, int maxcpu)
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{
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struct pmc_classdep *pcd;
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KASSERT(md != NULL, ("[tsc,%d] md is NULL", __LINE__));
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KASSERT(md->pmd_nclass >= 1, ("[tsc,%d] dubious md->nclass %d",
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__LINE__, md->pmd_nclass));
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tsc_pcpu = malloc(sizeof(struct tsc_cpu *) * maxcpu, M_PMC,
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M_ZERO|M_WAITOK);
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pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC];
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pcd->pcd_caps = PMC_CAP_READ;
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pcd->pcd_class = PMC_CLASS_TSC;
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pcd->pcd_num = TSC_NPMCS;
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pcd->pcd_ri = md->pmd_npmc;
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pcd->pcd_width = 64;
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pcd->pcd_allocate_pmc = tsc_allocate_pmc;
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pcd->pcd_config_pmc = tsc_config_pmc;
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pcd->pcd_describe = tsc_describe;
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pcd->pcd_get_config = tsc_get_config;
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pcd->pcd_get_msr = tsc_get_msr;
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pcd->pcd_pcpu_init = tsc_pcpu_init;
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pcd->pcd_pcpu_fini = tsc_pcpu_fini;
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pcd->pcd_read_pmc = tsc_read_pmc;
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pcd->pcd_release_pmc = tsc_release_pmc;
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pcd->pcd_start_pmc = tsc_start_pmc;
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pcd->pcd_stop_pmc = tsc_stop_pmc;
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pcd->pcd_write_pmc = tsc_write_pmc;
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md->pmd_npmc += TSC_NPMCS;
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return (0);
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}
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void
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pmc_tsc_finalize(struct pmc_mdep *md)
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{
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#ifdef INVARIANTS
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int i, ncpus;
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ncpus = pmc_cpu_max();
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for (i = 0; i < ncpus; i++)
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KASSERT(tsc_pcpu[i] == NULL, ("[tsc,%d] non-null pcpu cpu %d",
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__LINE__, i));
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KASSERT(md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC].pcd_class ==
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PMC_CLASS_TSC, ("[tsc,%d] class mismatch", __LINE__));
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#else
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(void) md;
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#endif
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free(tsc_pcpu, M_PMC);
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tsc_pcpu = NULL;
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}
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