Marcel Moolenaar dbb95048da Add cpu_flush_dcache() for use after non-DMA based I/O so that a ... possible future I-cache coherency operation can succeed. On ARM for example the L1 cache can be (is) virtually mapped, which means that any I/O that uses temporary mappings will not see the I-cache made coherent. On ia64 a similar behaviour has been observed. By flushing the D-cache, execution of binaries backed by md(4) and/or NFS work reliably. For Book-E (powerpc), execution over NFS exhibits SIGILL once in a while as well, though cpu_flush_dcache() hasn't been implemented yet. Doing an explicit D-cache flush as part of the non-DMA based I/O read operation eliminates the need to do it as part of the I-cache coherency operation itself and as such avoids pessimizing the DMA-based I/O read operations for which D-cache are already flushed/invalidated. It also allows future optimizations whereby the bcopy() followed by the D-cache flush can be integrated in a single operation, which could be implemented using on-chips DMA engines, by-passing the D-cache altogether.		2009-05-18 18:37:18 +00:00
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acpica	Catch up with ACPI-CA 20070320 import.	2007-03-22 18:16:43 +00:00
compile
conf	- Use "device\t" and "options \t" for consistency.	2009-05-10 00:00:25 +00:00
disasm	Fix disassembly of the invala, itc, itr and hint instructions	2007-10-16 02:49:40 +00:00
ia32	Add trivial implementation for the freebsd32_sysarch on ia64.	2009-04-01 19:23:07 +00:00
ia64	Add cpu_flush_dcache() for use after non-DMA based I/O so that a	2009-05-18 18:37:18 +00:00
include	Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizing	2009-04-20 12:59:23 +00:00
isa	Remove isa_irq_pending(). It's not used.	2009-04-24 03:43:20 +00:00
pci