4d9ac6c76f
level. The distinction was artificial. Some more movement around the deck charis is likely depending on the fallout from this one. Paths were corrected after the svn mv. Hope that's OK.
154 lines
4.9 KiB
C
154 lines
4.9 KiB
C
/*-
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* Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __IDTREG_H__
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#define __IDTREG_H__
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/* Interrupt controller */
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#define IDT_BASE_ICU 0x18038000
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#define ICU_IPEND2 0x00
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#define ICU_ITEST2 0x04
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#define ICU_IMASK2 0x08
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#define ICU_IPEND3 0x0C
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#define ICU_ITEST3 0x10
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#define ICU_IMASK3 0x14
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#define ICU_IPEND4 0x18
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#define ICU_ITEST4 0x1c
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#define ICU_IMASK4 0x20
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#define ICU_IPEND5 0x24
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#define ICU_ITEST5 0x28
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#define ICU_IMASK5 0x2c
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#define ICU_IPEND6 0x30
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#define ICU_ITEST6 0x34
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#define ICU_IMASK6 0x38
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#define ICU_NMIPS 0x3c
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#define IDT_BASE_GPIO 0x18050000
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#define GPIO_FUNC 0x00
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#define GPIO_CFG 0x04
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#define GPIO_DATA 0x08
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#define GPIO_ILEVEL 0x0C
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#define GPIO_ISTAT 0x10
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#define GPIO_NMIEN 0x14
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#define IDT_BASE_UART0 0x18058000
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/* PCI controller */
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#define IDT_BASE_PCI 0x18080000
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#define IDT_PCI_CNTL 0x00
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#define IDT_PCI_CNTL_EN 0x001
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#define IDT_PCI_CNTL_TNR 0x002
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#define IDT_PCI_CNTL_SCE 0x004
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#define IDT_PCI_CNTL_IEN 0x008
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#define IDT_PCI_CNTL_AAA 0x010
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#define IDT_PCI_CNTL_EAP 0x020
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#define IDT_PCI_CNTL_IGM 0x200
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#define IDT_PCI_STATUS 0x04
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#define IDT_PCI_STATUS_RIP 0x20000
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#define IDT_PCI_STATUS_MASK 0x08
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#define IDT_PCI_CFG_ADDR 0x0C
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#define IDT_PCI_CFG_DATA 0x10
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/* LBA stuff */
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#define IDT_PCI_LBA0 0x14
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#define IDT_PCI_LBA0_CNTL 0x18
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#define IDT_PCI_LBA_MSI 0x01
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#define IDT_PCI_LBA_SIZE_1MB (0x14 << 2)
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#define IDT_PCI_LBA_SIZE_2MB (0x15 << 2)
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#define IDT_PCI_LBA_SIZE_4MB (0x16 << 2)
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#define IDT_PCI_LBA_SIZE_8MB (0x17 << 2)
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#define IDT_PCI_LBA_SIZE_16MB (0x18 << 2)
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#define IDT_PCI_LBA_SIZE_32MB (0x19 << 2)
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#define IDT_PCI_LBA_SIZE_64MB (0x1A << 2)
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#define IDT_PCI_LBA_SIZE_128MB (0x1B << 2)
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#define IDT_PCI_LBA_SIZE_256MB (0x1C << 2)
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#define IDT_PCI_LBA_FE 0x80
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#define IDT_PCI_LBA_RT 0x100
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#define IDT_PCI_LBA0_MAP 0x1C
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#define IDT_PCI_LBA1 0x20
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#define IDT_PCI_LBA1_CNTL 0x24
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#define IDT_PCI_LBA1_MAP 0x28
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#define IDT_PCI_LBA2 0x2C
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#define IDT_PCI_LBA2_CNTL 0x30
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#define IDT_PCI_LBA2_MAP 0x34
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#define IDT_PCI_LBA3 0x38
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#define IDT_PCI_LBA3_CNTL 0x3C
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#define IDT_PCI_LBA3_MAP 0x40
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/* decoupled registers */
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#define IDT_PCI_DAC 0x44
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#define IDT_PCI_DAS 0x48
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#define IDT_PCI_DASM 0x4C
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#define IDT_PCI_TC 0x5C
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#define IDT_PCI_TC_RTIMER 0x10
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#define IDT_PCI_TC_DTIMER 0x08
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/* Messaging unit of PCI controller */
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#define IDT_PCI_IIC 0x8024
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#define IDT_PCI_IIM 0x8028
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#define IDT_PCI_OIC 0x8030
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#define IDT_PCI_OIM 0x8034
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/* PCI-related stuff */
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#define IDT_PCIMEM0_BASE 0x50000000
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#define IDT_PCIMEM0_SIZE 0x01000000
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#define IDT_PCIMEM1_BASE 0x60000000
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#define IDT_PCIMEM1_SIZE 0x10000000
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#define IDT_PCIMEM2_BASE 0x18C00000
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#define IDT_PCIMEM2_SIZE 0x00400000
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#define IDT_PCIMEM3_BASE 0x18800000
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#define IDT_PCIMEM3_SIZE 0x00100000
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/* Interrupts-related stuff */
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#define IRQ_BASE 8
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/* Convert <IPbit, irq_offset> pair to IRQ number */
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#define IP_IRQ(IPbit, offset) ((IPbit - 2) * 32 + (offset) + IRQ_BASE)
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/* The last one available IRQ */
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#define IRQ_END IP_IRQ(6, 31)
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#define ICU_GROUP_REG_OFFSET 0x0C
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#define ICU_IP(irq) (((irq) - IRQ_BASE) & 0x1f)
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#define ICU_IP_BIT(irq) (1 << ICU_IP(irq))
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#define ICU_GROUP(irq) (((irq) - IRQ_BASE) >> 5)
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#define ICU_GROUP_MASK_REG(group) \
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(ICU_IMASK2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
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#define ICU_GROUP_IPEND_REG(group) \
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(ICU_IPEND2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
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#define ICU_IRQ_MASK_REG(irq) \
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(ICU_IMASK2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
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#define ICU_IRQ_IPEND_REG(irq) \
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(ICU_IPEND2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
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#define PCI_IRQ_BASE IP_IRQ(6, 4)
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#define PCI_IRQ_END IP_IRQ(6, 7)
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#endif /* __IDTREG_H__ */
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