1093 lines
22 KiB
C
1093 lines
22 KiB
C
/*
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* Copyright (c) 1995 HD Associates, Inc.
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* All rights reserved.
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*
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* HD Associates, Inc.
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* PO Box 276
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* Pepperell, MA 01463-0276
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* dufault@hda.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by HD Associates, Inc.
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* 4. The name of HD Associates, Inc.
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* may not be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY HD ASSOCIATES ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Written by:
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* Peter Dufault
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* dufault@hda.com
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*
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* $FreeBSD$
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*
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*/
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#include "labpc.h"
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#include "opt_debug_outb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/bio.h>
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#define b_actf bio_queue.tqe_next
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#include <sys/dataacq.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#ifdef LOUTB
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#endif
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#include <i386/isa/isa_device.h>
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/* Miniumum timeout:
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*/
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#ifndef LABPC_MIN_TMO
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#define LABPC_MIN_TMO (hz)
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#endif
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#ifndef LABPC_DEFAULT_HERZ
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#define LABPC_DEFAULT_HERZ 500
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#endif
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/* Minor number:
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* UUSIDCCC
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* UU: Board unit.
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* S: SCAN bit for scan enable.
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* I: INTERVAL for interval support
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* D: 1: Digital I/O, 0: Analog I/O
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* CCC: Channel.
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* Analog (D==0):
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* input: channel must be 0 to 7.
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* output: channel must be 0 to 2
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* 0: D-A 0
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* 1: D-A 1
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* 2: Alternate channel 0 then 1
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*
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* Digital (D==1):
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* input: Channel must be 0 to 2.
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* output: Channel must be 0 to 2.
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*/
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/* Up to four boards:
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*/
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#define MAX_UNITS 4
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#define UNIT(dev) (((minor(dev) & 0xB0) >> 6) & 0x3)
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#define SCAN(dev) ((minor(dev) & 0x20) >> 5)
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#define INTERVAL(dev) ((minor(dev) & 0x10) >> 4)
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#define DIGITAL(dev) ((minor(dev) & 0x08) >> 3)
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/* Eight channels:
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*/
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#define CHAN(dev) (minor(dev) & 0x7)
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/* History: Derived from "dt2811.c" March 1995
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*/
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struct ctlr
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{
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int err;
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#define DROPPED_INPUT 0x100
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int base;
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int unit;
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unsigned long flags;
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#define BUSY 0x00000001
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u_char cr_image[4];
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u_short sample_us;
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struct bio start_queue; /* Start queue */
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struct bio *last; /* End of start queue */
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u_char *data;
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u_char *data_end;
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long tmo; /* Timeout in Herz */
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long min_tmo; /* Timeout in Herz */
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int cleared_intr;
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int gains[8];
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dev_t dev; /* Copy of device */
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void (*starter)(struct ctlr *ctlr, long count);
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void (*stop)(struct ctlr *ctlr);
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void (*intr)(struct ctlr *ctlr);
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/* Digital I/O support. Copy of Data Control Register for 8255:
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*/
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u_char dcr_val, dcr_is;
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/*
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* Handle for canceling our timeout.
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*/
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struct callout_handle ch;
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/* Device configuration structure:
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*/
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};
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#ifdef LOUTB
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/* loutb is a slow outb for debugging. The overrun test may fail
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* with this for some slower processors.
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*/
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static __inline void loutb(int port, u_char val)
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{
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outb(port, val);
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DELAY(1);
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}
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#else
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#define loutb(port, val) outb(port, val)
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#endif
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static struct ctlr **labpcs; /* XXX: Should be dynamic */
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/* CR_EXPR: A macro that sets the shadow register in addition to
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* sending out the data.
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*/
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#define CR_EXPR(LABPC, CR, EXPR) do { \
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(LABPC)->cr_image[CR - 1] EXPR ; \
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loutb(((LABPC)->base + ( (CR == 4) ? (0x0F) : (CR - 1))), ((LABPC)->cr_image[(CR - 1)])); \
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} while (0)
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#define CR_CLR(LABPC, CR) CR_EXPR(LABPC, CR, &=0)
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#define CR_REFRESH(LABPC, CR) CR_EXPR(LABPC, CR, &=0xff)
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#define CR_SET(LABPC, CR, EXPR) CR_EXPR(LABPC, CR, = EXPR)
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/* Configuration and Status Register Group.
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*/
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#define CR1(LABPC) ((LABPC)->base + 0x00) /* Page 4-5 */
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#define SCANEN 0x80
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#define GAINMASK 0x70
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#define GAIN(LABPC, SEL) do { \
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(LABPC)->cr_image[1 - 1] &= ~GAINMASK; \
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(LABPC)->cr_image[1 - 1] |= (SEL << 4); \
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loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
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} while (0)
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#define TWOSCMP 0x08
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#define MAMASK 0x07
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#define MA(LABPC, SEL) do { \
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(LABPC)->cr_image[1 - 1] &= ~MAMASK; \
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(LABPC)->cr_image[1 - 1] |= SEL; \
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loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
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} while (0)
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#define STATUS(LABPC) ((LABPC)->base + 0x00) /* Page 4-7 */
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#define LABPCPLUS 0x80
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#define EXTGATA0 0x40
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#define GATA0 0x20
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#define DMATC 0x10
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#define CNTINT 0x08
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#define OVERFLOW 0x04
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#define OVERRUN 0x02
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#define DAVAIL 0x01
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#define CR2(LABPC) ((LABPC)->base + 0x01) /* Page 4-9 */
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#define LDAC1 0x80
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#define LDAC0 0x40
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#define _2SDAC1 0x20
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#define _2SDAC0 0x10
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#define TBSEL 0x08
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#define SWTRIG 0x04
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#define HWTRIG 0x02
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#define PRETRIG 0x01
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#define SWTRIGGERRED(LABPC) ((LABPC->cr_image[1]) & SWTRIG)
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#define CR3(LABPC) ((LABPC)->base + 0x02) /* Page 4-11 */
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#define FIFOINTEN 0x20
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#define ERRINTEN 0x10
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#define CNTINTEN 0x08
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#define TCINTEN 0x04
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#define DIOINTEN 0x02
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#define DMAEN 0x01
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#define ALLINTEN 0x3E
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#define FIFOINTENABLED(LABPC) ((LABPC->cr_image[2]) & FIFOINTEN)
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#define CR4(LABPC) ((LABPC)->base + 0x0F) /* Page 4-13 */
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#define ECLKRCV 0x10
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#define SE_D 0x08
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#define ECKDRV 0x04
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#define EOIRCV 0x02
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#define INTSCAN 0x01
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/* Analog Input Register Group
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*/
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#define ADFIFO(LABPC) ((LABPC)->base + 0x0A) /* Page 4-16 */
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#define ADCLEAR(LABPC) ((LABPC)->base + 0x08) /* Page 4-18 */
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#define ADSTART(LABPC) ((LABPC)->base + 0x03) /* Page 4-19 */
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#define DMATCICLR(LABPC) ((LABPC)->base + 0x0A) /* Page 4-20 */
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/* Analog Output Register Group
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*/
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#define DAC0L(LABPC) ((LABPC)->base + 0x04) /* Page 4-22 */
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#define DAC0H(LABPC) ((LABPC)->base + 0x05) /* Page 4-22 */
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#define DAC1L(LABPC) ((LABPC)->base + 0x06) /* Page 4-22 */
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#define DAC1H(LABPC) ((LABPC)->base + 0x07) /* Page 4-22 */
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/* 8253 registers:
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*/
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#define A0DATA(LABPC) ((LABPC)->base + 0x14)
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#define A1DATA(LABPC) ((LABPC)->base + 0x15)
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#define A2DATA(LABPC) ((LABPC)->base + 0x16)
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#define AMODE(LABPC) ((LABPC)->base + 0x17)
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#define TICR(LABPC) ((LABPC)->base + 0x0c)
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#define B0DATA(LABPC) ((LABPC)->base + 0x18)
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#define B1DATA(LABPC) ((LABPC)->base + 0x19)
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#define B2DATA(LABPC) ((LABPC)->base + 0x1A)
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#define BMODE(LABPC) ((LABPC)->base + 0x1B)
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/* 8255 registers:
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*/
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#define PORTX(LABPC, X) ((LABPC)->base + 0x10 + X)
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#define PORTA(LABPC) PORTX(LABPC, 0)
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#define PORTB(LABPC) PORTX(LABPC, 1)
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#define PORTC(LABPC) PORTX(LABPC, 2)
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#define DCR(LABPC) ((LABPC)->base + 0x13)
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static int labpcattach(struct isa_device *dev);
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static int labpcprobe(struct isa_device *dev);
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struct isa_driver labpcdriver = {
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INTR_TYPE_TTY,
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labpcprobe,
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labpcattach,
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"labpc",
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0
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};
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COMPAT_ISA_DRIVER(labpc, labpcdriver);
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static d_open_t labpcopen;
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static d_close_t labpcclose;
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static d_ioctl_t labpcioctl;
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static d_strategy_t labpcstrategy;
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#define CDEV_MAJOR 66
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static struct cdevsw labpc_cdevsw = {
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/* open */ labpcopen,
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/* close */ labpcclose,
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/* read */ physread,
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/* write */ physwrite,
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/* ioctl */ labpcioctl,
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/* poll */ nopoll,
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/* mmap */ nommap,
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/* strategy */ labpcstrategy,
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/* name */ "labpc",
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/* maj */ CDEV_MAJOR,
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/* dump */ nodump,
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/* psize */ nopsize,
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/* flags */ 0,
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/* bmaj */ -1
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};
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static ointhand2_t labpcintr;
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static void start(struct ctlr *ctlr);
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static void
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bp_done(struct bio *bp, int err)
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{
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bp->bio_error = err;
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if (err || bp->bio_resid)
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{
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bp->bio_flags |= BIO_ERROR;
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}
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biodone(bp);
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}
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static void tmo_stop(void *p);
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static void
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done_and_start_next(struct ctlr *ctlr, struct bio *bp, int err)
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{
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bp->bio_resid = ctlr->data_end - ctlr->data;
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ctlr->data = 0;
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ctlr->start_queue.b_actf = bp->b_actf;
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bp_done(bp, err);
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untimeout(tmo_stop, ctlr, ctlr->ch);
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start(ctlr);
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}
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static __inline void
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ad_clear(struct ctlr *ctlr)
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{
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int i;
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loutb(ADCLEAR(ctlr), 0);
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for (i = 0; i < 10000 && (inb(STATUS(ctlr)) & GATA0); i++)
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;
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(void)inb(ADFIFO(ctlr));
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(void)inb(ADFIFO(ctlr));
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}
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/* reset: Reset the board following the sequence on page 5-1
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*/
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static __inline void
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reset(struct ctlr *ctlr)
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{
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int s = splhigh();
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CR_CLR(ctlr, 3); /* Turn off interrupts first */
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splx(s);
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CR_CLR(ctlr, 1);
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CR_CLR(ctlr, 2);
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CR_CLR(ctlr, 4);
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loutb(AMODE(ctlr), 0x34);
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loutb(A0DATA(ctlr),0x0A);
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loutb(A0DATA(ctlr),0x00);
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loutb(DMATCICLR(ctlr), 0x00);
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loutb(TICR(ctlr), 0x00);
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ad_clear(ctlr);
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loutb(DAC0L(ctlr), 0);
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loutb(DAC0H(ctlr), 0);
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loutb(DAC1L(ctlr), 0);
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loutb(DAC1H(ctlr), 0);
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ad_clear(ctlr);
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}
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/* overrun: slam the start convert register and OVERRUN should get set:
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*/
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static u_char
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overrun(struct ctlr *ctlr)
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{
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int i;
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u_char status = inb(STATUS(ctlr));
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for (i = 0; ((status & OVERRUN) == 0) && i < 100; i++)
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{
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loutb(ADSTART(ctlr), 1);
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status = inb(STATUS(ctlr));
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}
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return status;
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}
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static int
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labpcinit(void)
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{
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if (NLABPC > MAX_UNITS)
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return 0;
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labpcs = malloc(NLABPC * sizeof(struct ctlr *), M_DEVBUF, M_NOWAIT);
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if (labpcs)
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{
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bzero(labpcs, NLABPC * sizeof(struct ctlr *));
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return 1;
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}
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cdevsw_add(&labpc_cdevsw);
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return 0;
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}
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static int
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labpcprobe(struct isa_device *dev)
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{
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static int unit;
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struct ctlr scratch, *ctlr;
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u_char status;
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if (!labpcs)
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{
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if (labpcinit() == 0)
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{
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printf("labpcprobe: init failed\n");
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return 0;
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}
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}
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if (unit > NLABPC)
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{
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printf("Too many LAB-PCs. Reconfigure O/S.\n");
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return 0;
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}
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ctlr = &scratch; /* Need somebody with the right base for the macros */
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ctlr->base = dev->id_iobase;
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/* XXX: There really isn't a perfect way to probe this board.
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* Here is my best attempt:
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*/
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reset(ctlr);
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/* After reset none of these bits should be set:
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*/
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status = inb(STATUS(ctlr));
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if (status & (GATA0 | OVERFLOW | DAVAIL | OVERRUN))
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return 0;
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/* Now try to overrun the board FIFO and get the overrun bit set:
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*/
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status = overrun(ctlr);
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if ((status & OVERRUN) == 0) /* No overrun bit set? */
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return 0;
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/* Assume we have a board.
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*/
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reset(ctlr);
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if ( (labpcs[unit] = malloc(sizeof(struct ctlr), M_DEVBUF, M_NOWAIT)) )
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{
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struct ctlr *l = labpcs[unit];
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bzero(l, sizeof(struct ctlr));
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l->base = ctlr->base;
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dev->id_unit = l->unit = unit;
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unit++;
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return 0x20;
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}
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else
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{
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printf("labpc%d: Can't malloc.\n", unit);
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return 0;
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}
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}
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/* attach: Set things in a normal state.
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*/
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static int
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labpcattach(struct isa_device *dev)
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{
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struct ctlr *ctlr = labpcs[dev->id_unit];
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dev->id_ointr = labpcintr;
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callout_handle_init(&ctlr->ch);
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ctlr->sample_us = (1000000.0 / (double)LABPC_DEFAULT_HERZ) + .50;
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reset(ctlr);
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ctlr->min_tmo = LABPC_MIN_TMO;
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ctlr->dcr_val = 0x80;
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ctlr->dcr_is = 0x80;
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loutb(DCR(ctlr), ctlr->dcr_val);
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make_dev(&labpc_cdevsw, 0, 0, 0, 0600, "labpc%d", dev->id_unit);
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return 1;
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}
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/* Null handlers:
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*/
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static void null_intr (struct ctlr *ctlr) { }
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static void null_start(struct ctlr *ctlr, long count) { }
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static void null_stop (struct ctlr *ctlr) { }
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static __inline void
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trigger(struct ctlr *ctlr)
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{
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CR_EXPR(ctlr, 2, |= SWTRIG);
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}
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static void
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ad_start(struct ctlr *ctlr, long count)
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{
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if (!SWTRIGGERRED(ctlr)) {
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int chan = CHAN(ctlr->dev);
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CR_EXPR(ctlr, 1, &= ~SCANEN);
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CR_EXPR(ctlr, 2, &= ~TBSEL);
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|
|
MA(ctlr, chan);
|
|
GAIN(ctlr, ctlr->gains[chan]);
|
|
|
|
if (SCAN(ctlr->dev))
|
|
CR_EXPR(ctlr, 1, |= SCANEN);
|
|
|
|
loutb(AMODE(ctlr), 0x34);
|
|
loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
|
|
loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
|
|
loutb(AMODE(ctlr), 0x70);
|
|
|
|
ad_clear(ctlr);
|
|
trigger(ctlr);
|
|
}
|
|
|
|
ctlr->tmo = ((count + 16) * (long)ctlr->sample_us * hz) / 1000000 +
|
|
ctlr->min_tmo;
|
|
}
|
|
|
|
static void
|
|
ad_interval_start(struct ctlr *ctlr, long count)
|
|
{
|
|
int chan = CHAN(ctlr->dev);
|
|
int n_frames = count / (chan + 1);
|
|
|
|
if (!SWTRIGGERRED(ctlr)) {
|
|
CR_EXPR(ctlr, 1, &= ~SCANEN);
|
|
CR_EXPR(ctlr, 2, &= ~TBSEL);
|
|
|
|
MA(ctlr, chan);
|
|
GAIN(ctlr, ctlr->gains[chan]);
|
|
|
|
/* XXX: Is it really possible that you clear INTSCAN as
|
|
* the documentation says? That seems pretty unlikely.
|
|
*/
|
|
CR_EXPR(ctlr, 4, &= ~INTSCAN); /* XXX: Is this possible? */
|
|
|
|
/* Program the sample interval counter to run as fast as
|
|
* possible.
|
|
*/
|
|
loutb(AMODE(ctlr), 0x34);
|
|
loutb(A0DATA(ctlr), (u_char)(0x02));
|
|
loutb(A0DATA(ctlr), (u_char)(0x00));
|
|
loutb(AMODE(ctlr), 0x70);
|
|
|
|
/* Program the interval scanning counter to run at the sample
|
|
* frequency.
|
|
*/
|
|
loutb(BMODE(ctlr), 0x74);
|
|
loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
|
|
loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
|
|
CR_EXPR(ctlr, 1, |= SCANEN);
|
|
|
|
ad_clear(ctlr);
|
|
trigger(ctlr);
|
|
}
|
|
|
|
/* Each frame time takes two microseconds per channel times
|
|
* the number of channels being sampled plus the sample period.
|
|
*/
|
|
ctlr->tmo = ((n_frames + 16) *
|
|
((long)ctlr->sample_us + (chan + 1 ) * 2 ) * hz) / 1000000 +
|
|
ctlr->min_tmo;
|
|
}
|
|
|
|
static void
|
|
all_stop(struct ctlr *ctlr)
|
|
{
|
|
reset(ctlr);
|
|
}
|
|
|
|
static void
|
|
tmo_stop(void *p)
|
|
{
|
|
struct ctlr *ctlr = (struct ctlr *)p;
|
|
struct bio *bp;
|
|
|
|
int s = spltty();
|
|
|
|
if (ctlr == 0)
|
|
{
|
|
printf("labpc?: Null ctlr struct?\n");
|
|
splx(s);
|
|
return;
|
|
}
|
|
|
|
printf("labpc%d: timeout", ctlr->unit);
|
|
|
|
(*ctlr->stop)(ctlr);
|
|
|
|
bp = ctlr->start_queue.b_actf;
|
|
|
|
if (bp == 0) {
|
|
printf(", Null bp.\n");
|
|
splx(s);
|
|
return;
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
done_and_start_next(ctlr, bp, ETIMEDOUT);
|
|
|
|
splx(s);
|
|
}
|
|
|
|
static void ad_intr(struct ctlr *ctlr)
|
|
{
|
|
u_char status;
|
|
|
|
if (ctlr->cr_image[2] == 0)
|
|
{
|
|
if (ctlr->cleared_intr)
|
|
{
|
|
ctlr->cleared_intr = 0;
|
|
return;
|
|
}
|
|
|
|
printf("ad_intr (should not happen) interrupt with interrupts off\n");
|
|
printf("status %x, cr3 %x\n", inb(STATUS(ctlr)), ctlr->cr_image[2]);
|
|
return;
|
|
}
|
|
|
|
while ( (status = (inb(STATUS(ctlr)) & (DAVAIL|OVERRUN|OVERFLOW)) ) )
|
|
{
|
|
if ((status & (OVERRUN|OVERFLOW)))
|
|
{
|
|
struct bio *bp = ctlr->start_queue.b_actf;
|
|
|
|
printf("ad_intr: error: bp %p, data %p, status %x",
|
|
(void *)bp, (void *)ctlr->data, status);
|
|
|
|
if (status & OVERRUN)
|
|
printf(" Conversion overrun (multiple A-D trigger)");
|
|
|
|
if (status & OVERFLOW)
|
|
printf(" FIFO overflow");
|
|
|
|
printf("\n");
|
|
|
|
if (bp)
|
|
{
|
|
done_and_start_next(ctlr, bp, EIO);
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
printf("ad_intr: (should not happen) error between records\n");
|
|
ctlr->err = status; /* Set overrun condition */
|
|
return;
|
|
}
|
|
}
|
|
else /* FIFO interrupt */
|
|
{
|
|
struct bio *bp = ctlr->start_queue.b_actf;
|
|
|
|
if (ctlr->data)
|
|
{
|
|
*ctlr->data++ = inb(ADFIFO(ctlr));
|
|
if (ctlr->data == ctlr->data_end) /* Normal completion */
|
|
{
|
|
done_and_start_next(ctlr, bp, 0);
|
|
return;
|
|
}
|
|
}
|
|
else /* Interrupt with no where to put the data. */
|
|
{
|
|
printf("ad_intr: (should not happen) dropped input.\n");
|
|
(void)inb(ADFIFO(ctlr));
|
|
|
|
printf("bp %p, status %x, cr3 %x\n",
|
|
(void *)bp, status, ctlr->cr_image[2]);
|
|
|
|
ctlr->err = DROPPED_INPUT;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void labpcintr(int unit)
|
|
{
|
|
struct ctlr *ctlr = labpcs[unit];
|
|
(*ctlr->intr)(ctlr);
|
|
}
|
|
|
|
/* lockout_multiple_opens: Return whether or not we can open again, or
|
|
* if the new mode is inconsistent with an already opened mode.
|
|
* We only permit multiple opens for digital I/O now.
|
|
*/
|
|
|
|
static int
|
|
lockout_multiple_open(dev_t current, dev_t next)
|
|
{
|
|
return ! (DIGITAL(current) && DIGITAL(next));
|
|
}
|
|
|
|
static int
|
|
labpcopen(dev_t dev, int flags, int fmt, struct proc *p)
|
|
{
|
|
u_short unit = UNIT(dev);
|
|
|
|
struct ctlr *ctlr;
|
|
|
|
if (unit >= MAX_UNITS)
|
|
return ENXIO;
|
|
|
|
ctlr = labpcs[unit];
|
|
|
|
if (ctlr == 0)
|
|
return ENXIO;
|
|
|
|
/* Don't allow another open if we have to change modes.
|
|
*/
|
|
|
|
if ( (ctlr->flags & BUSY) == 0)
|
|
{
|
|
ctlr->flags |= BUSY;
|
|
|
|
reset(ctlr);
|
|
|
|
ctlr->err = 0;
|
|
ctlr->dev = dev;
|
|
|
|
ctlr->intr = null_intr;
|
|
ctlr->starter = null_start;
|
|
ctlr->stop = null_stop;
|
|
}
|
|
else if (lockout_multiple_open(ctlr->dev, dev))
|
|
return EBUSY;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
labpcclose(dev_t dev, int flags, int fmt, struct proc *p)
|
|
{
|
|
struct ctlr *ctlr = labpcs[UNIT(dev)];
|
|
|
|
(*ctlr->stop)(ctlr);
|
|
|
|
ctlr->flags &= ~BUSY;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Start: Start a frame going in or out.
|
|
*/
|
|
static void
|
|
start(struct ctlr *ctlr)
|
|
{
|
|
struct bio *bp;
|
|
|
|
if ((bp = ctlr->start_queue.b_actf) == 0)
|
|
{
|
|
/* We must turn off FIFO interrupts when there is no
|
|
* place to put the data. We have to get back to
|
|
* reading before the FIFO overflows.
|
|
*/
|
|
CR_EXPR(ctlr, 3, &= ~(FIFOINTEN|ERRINTEN));
|
|
ctlr->cleared_intr = 1;
|
|
ctlr->start_queue.bio_bcount = 0;
|
|
return;
|
|
}
|
|
|
|
ctlr->data = (u_char *)bp->bio_data;
|
|
ctlr->data_end = ctlr->data + bp->bio_bcount;
|
|
|
|
if (ctlr->err)
|
|
{
|
|
printf("labpc start: (should not happen) error between records.\n");
|
|
done_and_start_next(ctlr, bp, EIO);
|
|
return;
|
|
}
|
|
|
|
if (ctlr->data == 0)
|
|
{
|
|
printf("labpc start: (should not happen) NULL data pointer.\n");
|
|
done_and_start_next(ctlr, bp, EIO);
|
|
return;
|
|
}
|
|
|
|
|
|
(*ctlr->starter)(ctlr, bp->bio_bcount);
|
|
|
|
if (!FIFOINTENABLED(ctlr)) /* We can store the data again */
|
|
{
|
|
CR_EXPR(ctlr, 3, |= (FIFOINTEN|ERRINTEN));
|
|
|
|
/* Don't wait for the interrupts to fill things up.
|
|
*/
|
|
(*ctlr->intr)(ctlr);
|
|
}
|
|
|
|
ctlr->ch = timeout(tmo_stop, ctlr, ctlr->tmo);
|
|
}
|
|
|
|
static void
|
|
ad_strategy(struct bio *bp, struct ctlr *ctlr)
|
|
{
|
|
int s;
|
|
|
|
s = spltty();
|
|
bp->b_actf = NULL;
|
|
|
|
if (ctlr->start_queue.bio_bcount)
|
|
{
|
|
ctlr->last->b_actf = bp;
|
|
ctlr->last = bp;
|
|
}
|
|
else
|
|
{
|
|
ctlr->start_queue.bio_bcount = 1;
|
|
ctlr->start_queue.b_actf = bp;
|
|
ctlr->last = bp;
|
|
start(ctlr);
|
|
}
|
|
splx(s);
|
|
}
|
|
|
|
/* da_strategy: Send data to the D-A. The CHAN field should be
|
|
* 0: D-A port 0
|
|
* 1: D-A port 1
|
|
* 2: Alternate port 0 then port 1
|
|
*
|
|
* XXX:
|
|
*
|
|
* 1. There is no state for CHAN field 2:
|
|
* the first sample in each buffer goes to channel 0.
|
|
*
|
|
* 2. No interrupt support yet.
|
|
*/
|
|
static void
|
|
da_strategy(struct bio *bp, struct ctlr *ctlr)
|
|
{
|
|
int len;
|
|
u_char *data;
|
|
int port;
|
|
int i;
|
|
|
|
switch(CHAN(bp->bio_dev))
|
|
{
|
|
case 0:
|
|
port = DAC0L(ctlr);
|
|
break;
|
|
|
|
case 1:
|
|
port = DAC1L(ctlr);
|
|
break;
|
|
|
|
case 2: /* Device 2 handles both ports interleaved. */
|
|
if (bp->bio_bcount <= 2)
|
|
{
|
|
port = DAC0L(ctlr);
|
|
break;
|
|
}
|
|
|
|
len = bp->bio_bcount / 2;
|
|
data = (u_char *)bp->bio_data;
|
|
|
|
for (i = 0; i < len; i++)
|
|
{
|
|
loutb(DAC0H(ctlr), *data++);
|
|
loutb(DAC0L(ctlr), *data++);
|
|
loutb(DAC1H(ctlr), *data++);
|
|
loutb(DAC1L(ctlr), *data++);
|
|
}
|
|
|
|
bp->bio_resid = bp->bio_bcount & 3;
|
|
bp_done(bp, 0);
|
|
return;
|
|
|
|
default:
|
|
bp_done(bp, ENXIO);
|
|
return;
|
|
}
|
|
|
|
/* Port 0 or 1 falls through to here.
|
|
*/
|
|
if (bp->bio_bcount & 1) /* Odd transfers are illegal */
|
|
bp_done(bp, EIO);
|
|
|
|
len = bp->bio_bcount;
|
|
data = (u_char *)bp->bio_data;
|
|
|
|
for (i = 0; i < len; i++)
|
|
{
|
|
loutb(port + 1, *data++);
|
|
loutb(port, *data++);
|
|
}
|
|
|
|
bp->bio_resid = 0;
|
|
|
|
bp_done(bp, 0);
|
|
}
|
|
|
|
/* Input masks for MODE 0 of the ports treating PC as a single
|
|
* 8 bit port. Set these bits to set the port to input.
|
|
*/
|
|
/* A B lowc highc combined */
|
|
static u_char set_input[] = { 0x10, 0x02, 0x01, 0x08, 0x09 };
|
|
|
|
static void flush_dcr(struct ctlr *ctlr)
|
|
{
|
|
if (ctlr->dcr_is != ctlr->dcr_val)
|
|
{
|
|
loutb(DCR(ctlr), ctlr->dcr_val);
|
|
ctlr->dcr_is = ctlr->dcr_val;
|
|
}
|
|
}
|
|
|
|
/* do: Digital output
|
|
*/
|
|
static void
|
|
digital_out_strategy(struct bio *bp, struct ctlr *ctlr)
|
|
{
|
|
int len;
|
|
u_char *data;
|
|
int port;
|
|
int i;
|
|
int chan = CHAN(bp->bio_dev);
|
|
|
|
ctlr->dcr_val &= ~set_input[chan]; /* Digital out: Clear bit */
|
|
flush_dcr(ctlr);
|
|
|
|
port = PORTX(ctlr, chan);
|
|
|
|
len = bp->bio_bcount;
|
|
data = (u_char *)bp->bio_data;
|
|
|
|
for (i = 0; i < len; i++)
|
|
{
|
|
loutb(port, *data++);
|
|
}
|
|
|
|
bp->bio_resid = 0;
|
|
|
|
bp_done(bp, 0);
|
|
}
|
|
|
|
/* digital_in_strategy: Digital input
|
|
*/
|
|
static void
|
|
digital_in_strategy(struct bio *bp, struct ctlr *ctlr)
|
|
{
|
|
int len;
|
|
u_char *data;
|
|
int port;
|
|
int i;
|
|
int chan = CHAN(bp->bio_dev);
|
|
|
|
ctlr->dcr_val |= set_input[chan]; /* Digital in: Set bit */
|
|
flush_dcr(ctlr);
|
|
port = PORTX(ctlr, chan);
|
|
|
|
len = bp->bio_bcount;
|
|
data = (u_char *)bp->bio_data;
|
|
|
|
for (i = 0; i < len; i++)
|
|
{
|
|
*data++ = inb(port);
|
|
}
|
|
|
|
bp->bio_resid = 0;
|
|
|
|
bp_done(bp, 0);
|
|
}
|
|
|
|
|
|
static void
|
|
labpcstrategy(struct bio *bp)
|
|
{
|
|
struct ctlr *ctlr = labpcs[UNIT(bp->bio_dev)];
|
|
|
|
if (DIGITAL(bp->bio_dev)) {
|
|
if (bp->bio_cmd == BIO_READ) {
|
|
ctlr->starter = null_start;
|
|
ctlr->stop = all_stop;
|
|
ctlr->intr = null_intr;
|
|
digital_in_strategy(bp, ctlr);
|
|
}
|
|
else
|
|
{
|
|
ctlr->starter = null_start;
|
|
ctlr->stop = all_stop;
|
|
ctlr->intr = null_intr;
|
|
digital_out_strategy(bp, ctlr);
|
|
}
|
|
}
|
|
else {
|
|
if (bp->bio_cmd == BIO_READ) {
|
|
|
|
ctlr->starter = INTERVAL(ctlr->dev) ? ad_interval_start : ad_start;
|
|
ctlr->stop = all_stop;
|
|
ctlr->intr = ad_intr;
|
|
ad_strategy(bp, ctlr);
|
|
}
|
|
else
|
|
{
|
|
ctlr->starter = null_start;
|
|
ctlr->stop = all_stop;
|
|
ctlr->intr = null_intr;
|
|
da_strategy(bp, ctlr);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
labpcioctl(dev_t dev, u_long cmd, caddr_t arg, int mode, struct proc *p)
|
|
{
|
|
struct ctlr *ctlr = labpcs[UNIT(dev)];
|
|
|
|
switch(cmd)
|
|
{
|
|
case AD_MICRO_PERIOD_SET:
|
|
{
|
|
/* XXX I'm only supporting what I have to, which is
|
|
* no slow periods. You can't get any slower than 15 Hz
|
|
* with the current setup. To go slower you'll need to
|
|
* support TCINTEN in CR3.
|
|
*/
|
|
|
|
long sample_us = *(long *)arg;
|
|
|
|
if (sample_us > 65535)
|
|
return EIO;
|
|
|
|
ctlr->sample_us = sample_us;
|
|
return 0;
|
|
}
|
|
|
|
case AD_MICRO_PERIOD_GET:
|
|
*(long *)arg = ctlr->sample_us;
|
|
return 0;
|
|
|
|
case AD_NGAINS_GET:
|
|
*(int *)arg = 8;
|
|
return 0;
|
|
|
|
case AD_NCHANS_GET:
|
|
*(int *)arg = 8;
|
|
return 0;
|
|
|
|
case AD_SUPPORTED_GAINS:
|
|
{
|
|
static double gains[] = {1., 1.25, 2., 5., 10., 20., 50., 100.};
|
|
copyout(gains, *(caddr_t *)arg, sizeof(gains));
|
|
|
|
return 0;
|
|
}
|
|
|
|
case AD_GAINS_SET:
|
|
{
|
|
copyin(*(caddr_t *)arg, ctlr->gains, sizeof(ctlr->gains));
|
|
return 0;
|
|
}
|
|
|
|
case AD_GAINS_GET:
|
|
{
|
|
copyout(ctlr->gains, *(caddr_t *)arg, sizeof(ctlr->gains));
|
|
return 0;
|
|
}
|
|
|
|
default:
|
|
return ENOTTY;
|
|
}
|
|
}
|