369 lines
16 KiB
C
369 lines
16 KiB
C
/*
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* Copyright (c) 1993, 1994, 1995
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* Rodney W. Grimes, Milwaukie, Oregon 97222. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Rodney W. Grimes.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY RODNEY W. GRIMES ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL RODNEY W. GRIMES BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: if_ixreg.h,v 1.6 1995/05/30 08:02:17 rgrimes Exp $
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*/
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/*
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* These really belong some place else, but I can't find them right
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* now. I'll look again latter
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*/
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#define ETHER_ADDRESS_LENGTH 6 /* Length of an ethernet address */
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#define ETHER_HEADER_LENGTH 14 /* Length of an ethernet header */
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#define ETHER_DATA_LENGTH ETHERMTU
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#define ETHER_CRC_LENGTH 4
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#define ETHER_MIN_LENGTH 64 /* Minimum length of an ethernet packet */
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#define ETHER_MAX_LENGTH (ETHER_HEADER_LENGTH + \
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ETHERMTU + \
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ETHER_CRC_LENGTH)
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#define IX_IO_PORTS 16 /* Number of I/O ports used, note
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* this is not true, due to shadow
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* ports at 400X,800X and C00X
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*/
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#define dxreg 0x00 /* Data transfer register Word R/W */
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#define wrptr 0x02 /* Write address pointer Word R/W */
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#define rdptr 0x04 /* Read address pointer Word R/W */
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#define ca_ctrl 0x06 /* Channel attention control Byte R/W */
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#define sel_irq 0x07 /* IRQ select Byte R/W */
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#define IRQ_ENABLE 0x08 /* Enable board interrupts */
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#define smb_ptr 0x08 /* Shadow memory bank pointer Word R/W */
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#define memdec 0x0A /* Memory address decode Byte W */
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#define memctrl 0x0B /* Memory mapped control Byte R/W */
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#define MEMCTRL_UNUSED 0x83 /* Unused bits */
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#define MEMCTRL_MEMMEG 0x60 /* Which megabyte of memory, 0, E or F */
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#define MEMCTRL_FMCS16 0x10 /* MEMCS16- for F000 */
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#define MEMCTRL_MEMADJ 0xC0 /* memory adjust value */
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#define mempc 0x0C /* MEMCS16- page control Byte R/W */
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#define config 0x0D /* Configuration, test Byte R/W */
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#define BART_LINK 0x01 /* link integrity active, TPE */
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#define BART_LOOPBACK 0x02 /* Loopback, 0=none, 1=loopback */
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#define SLOT_WIDTH 0x04 /* 0 = 8bit, 1 = 16bit */
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#define BART_USEWIDTH 0x08 /* use SLOT_WIDTH for bus size */
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#define BART_IOCHRDY_LATE 0x10 /* iochrdy late control bit */
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#define BART_IO_TEST_EN 0x20 /* enable iochrdy timing test */
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#define BART_IO_RESULT 0x40 /* result of the iochrdy test */
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#define BART_MCS16_TEST 0x80 /* enable memcs16 select test */
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#define ee_ctrl 0x0E /* EEPROM control, reset Byte R/W */
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#define EENORMAL 0x00 /* normal state of ee_ctrl */
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#define EESK 0x01 /* EEPROM clock bit */
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#define EECS 0x02 /* EEPROM chip select */
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#define EEDI 0x04 /* EEPROM data in bit (write EEPROM) */
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#define EEDO 0x08 /* EEPROM data out bit (read EEPROM) */
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#define EEUNUSED 0x30 /* unused bits in ee_ctrl */
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#define GA_RESET 0x40 /* BART ASIC chip reset pin */
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#define I586_RESET 0x80 /* 82586 chip reset pin */
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#define memectrl 0x0F /* Memory control, E000h seg Byte W */
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#define autoid 0x0F /* Auto ID register Byte R */
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#define BOARDID 0xBABA /* Intel PCED board ID for EtherExpress */
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#define eeprom_opsize1 0x03 /* Size of opcodes for r/w/e */
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#define eeprom_read_op 0x06 /* EEPROM read op code */
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#define eeprom_write_op 0x05 /* EEPROM write op code */
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#define eeprom_erase_op 0x07 /* EEPROM erase op code */
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#define eeprom_opsize2 0x05 /* Size of opcodes for we/wdr */
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#define eeprom_wenable_op 0x13 /* EEPROM write enable op code */
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#define eeprom_wdisable_op 0x10 /* EEPROM write disable op code */
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#define eeprom_addr_size 0x06 /* Size of EEPROM address */
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/* These are the locations in the EEPROM */
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#define eeprom_config1 0x00 /* Configuration register 1 */
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#define CONNECT_BNCTPE 0x1000 /* 0 = AUI, 1 = BNC/TPE */
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#define IRQ 0xE000 /* Encoded IRQ */
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#define IRQ_SHIFT 13 /* To shift IRQ to lower bits */
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#define eeprom_lock_address 0x01 /* contains the lock bit */
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#define EEPROM_LOCKED 0x01 /* means that it is locked */
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#define eeprom_enetaddr_low 0x02 /* Ethernet address, low word */
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#define eeprom_enetaddr_mid 0x03 /* Ethernet address, middle word */
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#define eeprom_enetaddr_high 0x04 /* Ethernet address, high word */
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#define eeprom_config2 0x05 /* Configuration register 2 */
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#define CONNECT_TPE 0x0001 /* 0 = BNC, 1 = TPE */
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/* this converts a kernal virtual address to a board offset */
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#define KVTOBOARD(addr) ((int)addr - (int)sc->maddr)
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#define BOARDTOKV(addr) ((int)addr + (int)sc->maddr)
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/* XXX This belongs is ic/i825x6.h, but is here for editing for now */
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#define INTEL586NULL 0xFFFF /* NULL pointer for 82586 */
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#define INTEL596NULL 0xFFFFFFFF /* NULL pointer for 82596 */
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/*
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* Layout of memory for the 825x6 chip:
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* Low: Control Blocks
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* Transmit Frame Descriptor(s)
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* Transmit Frame Buffer(s)
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* Receive Frame Descriptors
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* Receive Frames
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* SCB_ADDR System Control Block
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* ISCP_ADDR Intermediate System Configuration Pointer
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* High: SCP_ADDR System Configuration Pointer
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*/
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#define SCP_ADDR (sc->msize - sizeof(scp_t))
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#define ISCP_ADDR (SCP_ADDR - sizeof(iscp_t))
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#define SCB_ADDR (ISCP_ADDR - sizeof(scb_t))
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#define TB_COUNT 3 /* How many transfer buffers in the TFA */
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#define TB_SIZE (ETHER_MAX_LENGTH) /* size of transmit buffer */
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#define TFA_START 0x0000 /* Start of the TFA */
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#define TFA_SIZE (TB_COUNT * \
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(sizeof(cb_transmit_t) + sizeof(tbd_t) + TB_SIZE))
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#define RFA_START (TFA_SIZE)
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#define RFA_SIZE (SCP_ADDR - RFA_START)
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#define RB_SIZE (ETHER_MAX_LENGTH) /* size of receive buffer */
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typedef struct /* System Configuration Pointer */
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{
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u_short unused1; /* should be zeros for 82596 compatibility */
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u_short sysbus; /* width of the 82586 data bus 0=16, 1=8 */
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u_short unused2; /* should be zeros for 82596 compatibility */
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u_short unused3; /* should be zeros for 82596 compatibility */
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u_long iscp; /* iscp address (24bit 586, 32bit 596) */
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} scp_t;
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typedef struct /* Intermediate System Configuration Pointer */
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{
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volatile
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u_short busy; /* Set to 1 by host before its first CA,
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cleared by 82586 after reading */
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#define ISCP_BUSY 0x01 /* 82586 is busy reading the iscp */
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u_short scb_offset; /* Address of System Control Block */
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u_long scb_base; /* scb base address (24bit 586, 32bit 596) */
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} iscp_t;
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typedef struct /* System Control Block */
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{
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volatile
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u_short status; /* status bits */
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#define SCB_RUS_MASK 0x0070 /* receive unit status mask */
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#define SCB_RUS_IDLE 0x0000 /* receive unit status idle */
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#define SCB_RUS_SUSP 0x0010 /* receive unit status suspended */
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#define SCB_RUS_NRSC 0x0020 /* receive unit status no resources */
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#define SCB_RUS_READY 0x0040 /* receive unit status ready */
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#define SCB_CUS_MASK 0x0700 /* command unit status mask */
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#define SCB_CUS_IDLE 0x0000 /* command unit status idle */
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#define SCB_CUS_SUSP 0x0100 /* command unit status suspended */
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#define SCB_CUS_ACT 0x0200 /* command unit status active */
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#define SCB_STAT_MASK 0xF000 /* command unit status mask */
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#define SCB_STAT_RNR 0x1000 /* receive unit left the ready state */
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#define SCB_STAT_CNA 0x2000 /* command unit left the active state */
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#define SCB_STAT_FR 0x4000 /* the ru finished receiving a frame */
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#define SCB_STAT_CX 0x8000 /* the cu finished executing a command
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with its I (interrupt) bit set */
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#define SCB_STAT_NULL 0x0000 /* used to clear the status work */
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u_short command; /* command bits */
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#define SCB_RUC_MASK 0x0070 /* receive unit command mask */
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#define SCB_RUC_NOP 0x0000 /* receive unit command nop */
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#define SCB_RUC_START 0x0010 /* receive unit command start */
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#define SCB_RUC_RESUME 0x0020 /* receive unit command resume */
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#define SCB_RUC_SUSP 0x0030 /* receive unit command suspend */
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#define SCB_RUC_ABORT 0x0040 /* receive unit command abort */
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#define SCB_RESET 0x0080 /* reset the chip, same as hardware reset */
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#define SCB_CUC_MASK 0x0700 /* command unit command mask */
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#define SCB_CUC_NOP 0x0000 /* command unit command nop */
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#define SCB_CUC_START 0x0100 /* start execution of the first command */
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#define SCB_CUC_RESUME 0x0200 /* resume execution of the next command */
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#define SCB_CUC_SUSP 0x0300 /* suspend execution after the current command */
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#define SCB_CUC_ABORT 0x0400 /* abort execution of the current command */
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#define SCB_ACK_MASK 0xF000 /* command unit acknowledge mask */
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#define SCB_ACK_RNR 0x1000 /* ack receive unit left the ready state */
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#define SCB_ACK_CNA 0x2000 /* ack command unit left the active state */
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#define SCB_ACK_FR 0x4000 /* ack the ru finished receiving a frame */
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#define SCB_ACK_CX 0x8000 /* ack the cu finished executing a command
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with its I (interrupt) bit set */
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u_short cbl_offset; /* first command block on the cbl */
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u_short rfa_offset; /* receive frame area */
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volatile
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u_short crc_errors; /* frame was aligned, but bad crc */
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volatile
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u_short aln_errors; /* frame was not aligned, and had bad crc */
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volatile
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u_short rsc_errors; /* did not have resources to receive */
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volatile
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u_short ovr_errors; /* system bus was not available to receive */
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} scb_t;
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typedef struct /* command block - nop (also the common part of cb's */
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{
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volatile
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u_short status; /* status bits */
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#define CB_COLLISIONS 0x000F /* the number of collisions that occured */
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#define CB_BIT4 0x0010 /* reserved by intel */
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#define CB_EXCESSCOLL 0x0020 /* the number of collisions > MAX allowed */
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#define CB_HEARTBEAT 0x0040 /* */
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#define CB_DEFER 0x0080 /* had to defer due to trafic */
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#define CB_DMAUNDER 0x0100 /* dma underrun */
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#define CB_NOCTS 0x0200 /* lost clear to send */
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#define CB_NOCS 0x0400 /* lost carrier sense */
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#define CB_LATECOLL 0x0800 /* late collision occured (82596 only) */
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#define CB_ABORT 0x1000 /* command was aborted by CUC abort command */
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#define CB_OK 0x2000 /* command executed without error */
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#define CB_BUSY 0x4000 /* command is being executed */
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#define CB_COMPLETE 0x8000 /* command completed */
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u_short command; /* command bits */
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#define CB_CMD_MASK 0x0007 /* command mask */
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#define CB_CMD_NOP 0x0000 /* nop command */
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#define CB_CMD_IAS 0x0001 /* individual address setup command */
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#define CB_CMD_CONF 0x0002 /* configure command */
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#define CB_CMD_MCAS 0x0003 /* multicast address setup command */
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#define CB_CMD_TRANSMIT 0x0004 /* transmit command */
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#define CB_CMD_TDR 0x0005 /* time domain reflectometry command */
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#define CB_CMD_DUMP 0x0006 /* dump command */
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#define CB_CMD_DIAGNOSE 0x0007 /* diagnose command */
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#define CB_CMD_INT 0x2000 /* interrupt when command completed */
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#define CB_CMD_SUSP 0x4000 /* suspend CU when command completed */
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#define CB_CMD_EL 0x8000 /* end of the command block list */
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u_short next; /* pointer to the next cb */
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} cb_t;
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typedef struct /* command block - individual address setup command */
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{
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cb_t common; /* common part of all command blocks */
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u_char source[ETHER_ADDRESS_LENGTH];
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/* ethernet hardware address */
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} cb_ias_t;
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typedef struct /* command block - configure command */
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{
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cb_t common; /* common part of all command blocks */
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u_char byte[12]; /* ZZZ this is ugly, but it works */
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} cb_configure_t;
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typedef struct /* command block - multicast address setup command */
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{
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cb_t common; /* common part of all command blocks */
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} cb_mcas_t;
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typedef struct /* command block - transmit command */
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{
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cb_t common; /* common part of all command blocks */
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u_short tbd_offset; /* transmit buffer descriptor offset */
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u_char destination[ETHER_ADDRESS_LENGTH];
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/* ethernet destination address field */
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u_short length; /* ethernet length field */
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u_char byte[16]; /* XXX stupid fill tell I fix the ixinit
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* code for the special cb's */
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} cb_transmit_t;
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typedef struct /* command block - tdr command */
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{
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cb_t common; /* common part of all command blocks */
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} cb_tdr_t;
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typedef struct /* command block - dump command */
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{
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cb_t common; /* common part of all command blocks */
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} cb_dump_t;
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typedef struct /* command block - diagnose command */
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{
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cb_t common; /* common part of all command blocks */
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} cb_diagnose_t;
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typedef struct /* Transmit Buffer Descriptor */
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{
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volatile
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u_short act_count; /* size of buffer actual count of valid bytes */
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#define TBD_STAT_EOF 0x8000 /* end of frame */
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u_short next; /* pointer to the next tbd */
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u_long buffer; /* transmit buffer address (24bit 586, 32bit 596) */
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} tbd_t;
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typedef struct /* Receive Frame Descriptor */
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{
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volatile
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u_short status; /* status bits */
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#define RFD_BUSY 0x4000 /* frame is being received */
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#define RFD_COMPLETE 0x8000 /* this frame is complete */
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u_short command; /* command bits */
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#define RFD_CMD_SUSP 0x4000 /* suspend the ru after this rfd is used */
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#define RFD_CMD_EL 0x8000 /* end of the rfd list */
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u_short next; /* pointer to the next rfd */
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u_short rbd_offset; /* pointer to the first rbd for this frame */
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u_char destination[6]; /* ethernet destination address */
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u_char source[6]; /* ethernet source address */
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u_short length; /* ethernet length field */
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} rfd_t;
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typedef struct /* Receive Buffer Descriptor */
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{
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volatile
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u_short act_count; /* Actual Count (size) and status bits */
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#define RBD_STAT_SIZE 0x3FFF /* size mask */
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#define RBD_STAT_VALID 0x4000 /* act_count field is valid */
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#define RBD_STAT_EOF 0x8000 /* end of frame */
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u_short next; /* pointer to the next rbd */
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u_long buffer; /* receive buffer address */
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u_short size; /* size of buffer in bytes, must be even */
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#define RBD_SIZE_EL 0x8000 /* end of rbd list */
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} rbd_t;
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/*
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* Ethernet software status per interface.
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*
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* Each interface is referenced by a network interface structure,
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* arpcom.ac_if, which the routing code uses to locate the interface.
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* This structure contains the output queue for the interface, its address, ...
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*/
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typedef struct
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{
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struct arpcom arpcom; /* Ethernet common part see net/if.h */
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int iobase; /* I/O base address for this interface */
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caddr_t maddr; /* Memory base address for this interface */
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int msize; /* Size of memory */
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int flags; /* Software state */
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#define IXF_NONE 0x00000000 /* Clear all flags */
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#define IXF_INITED 0x00000001 /* Device has been inited */
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#define IXF_BPFATTACHED 0x80000000 /* BPF has been attached */
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int connector; /* Type of connector used on board */
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#define AUI 0x00 /* Using AUI connector */
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#define BNC 0x01 /* Using BNC connector */
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#define TPE 0x02 /* Using TPE connector */
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u_short irq_encoded; /* Encoded interrupt for use on bart */
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int width; /* Width of slot the board is in, these
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* constants are defined to match what
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* the 82586/596 wants in scp->sysbus */
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#define WIDTH_8 0x01 /* 8-bit slot */
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#define WIDTH_16 0x00 /* 16-bit slot */
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cb_t *cb_head; /* head of cb list */
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cb_t *cb_tail; /* tail of cb list */
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tbd_t *tbd_head; /* head of the tbd list */
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tbd_t *tbd_tail; /* tail of the tbd list */
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rfd_t *rfd_head; /* head of the rfd list */
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rfd_t *rfd_tail; /* tail of the rfd list */
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rbd_t *rbd_head; /* head of the rbd list */
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rbd_t *rbd_tail; /* tail of the rbd list */
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struct kern_devconf kdc;
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} ix_softc_t;
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