freebsd-nq/sys/ia64
Marcel Moolenaar dfcba5aae3 Put an instruction group break between the move to ar.rnat and the
move to ar.rsc. The RSE must be in enforced lazy mode when writing
to RSE modifyable registers. In this case we restore the RSE NaT
collection register ar.rnat. I have seen 2 general exception faults
on pluto1 now that indicate that the move to ar.rsc has already
happened prior to the move to ar.rnat, meaning that the RSE is not
in enforced lazy mode anymore. The ia64 dependency and instruction
ordering rules seem to allow having both registers written to in
the same instruction group, provided ar.rsc is written to later than
ar.rnat (based on the ordering semantics). It appears that we may
be pushing our luck. For now, put them in seperate cycles (by means
of the instruction group break). If we ever get a general exception
fault on the move to ar.rnat again, we have definite proof that
something else is fishy.
2003-08-13 02:49:50 +00:00
..
acpica Don't hardcode the address of the local (S)APIC (aka processor 2003-01-05 22:14:30 +00:00
compile Don't need the .keep_me files. Obrien and I committed past each other. 2001-07-01 23:35:44 +00:00
conf Remove INVARIANT* and WITNESS. This makes the simulator much more 2003-07-25 07:52:20 +00:00
ia32 Revamp of the syscall path, exception and context handling. The 2003-05-16 21:26:42 +00:00
ia64 Put an instruction group break between the move to ar.rnat and the 2003-08-13 02:49:50 +00:00
include Expand inline the relevant parts of src/COPYRIGHT for Matt Dillon's 2003-08-12 23:24:05 +00:00
isa Mega busdma API commit. 2003-07-01 15:52:06 +00:00
pci Delete legacy pcib code - we can't possibly work without acpi on ia64. 2001-10-06 10:09:57 +00:00