Ed Maste 3f8e262e8c Workaround for PCIe 4GB boundary issue ... Enforce a boundary of no more than 4GB - transfers crossing a 4GB boundary can lead to data corruption due to PCIe limitations. This change is a less-intrusive workaround that can be quickly merged back to older branches; a cleaner implementation will arrive in HEAD later but may require KPI changes. This change is based on a suggestion by jhb@. Reviewed by: scottl, jhb Sponsored by: Sandvine Incorporated MFC after: 3 days		2012-02-28 19:42:40 +00:00
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acpica	Fix a few bugs in the SRAT parsing code:	2012-01-03 20:53:58 +00:00
bios	Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.	2011-11-07 15:43:11 +00:00
cpufreq	Fix apparent logic reversal in setting the 'auto_mode' flag.	2012-02-26 21:24:27 +00:00
include	Copy amd64 endian.h to x86 and merge with i386 endian.h. Replace	2012-02-28 19:39:54 +00:00
isa	Implement boot-time TSC synchronization test for SMP. This test is executed	2011-05-09 17:34:00 +00:00
pci	- There's no need to overwrite the default device method with the default	2011-11-22 21:28:20 +00:00
x86	Workaround for PCIe 4GB boundary issue	2012-02-28 19:42:40 +00:00