Ruslan Bukin fcc3a0f630 Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build. ...

Sponsored by:	DARPA, AFRL

2019-05-08 16:06:54 +00:00

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conf

Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build.

2019-05-08 16:06:54 +00:00

include

Provide a template for busdma code for RISC-V.

2019-05-07 13:41:43 +00:00

riscv

Disable interrupts first and then set spinlock_count to 1.

2019-05-07 14:32:17 +00:00