cdf4ec6873
Use driver settable callbacks for handling of: - core post reset - reading actual port speed Typically, OTG enabled EHCI cores wants setting of USBMODE register, but this register is not defined in EHCI specification and different cores can have it on different offset. Also, for cores with TT extension, actual port speed must be determinable. But again, EHCI specification not covers this so this patch provides function for two most common variant of speed bits layout. Reviewed by: hselasky Differential Revision: https://reviews.freebsd.org/D5088
376 lines
10 KiB
C
376 lines
10 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* FDT attachment driver for the USB Enhanced Host Controller.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include <sys/stdint.h>
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#include <sys/stddef.h>
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#include <sys/param.h>
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#include <sys/queue.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <sys/sysctl.h>
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#include <sys/sx.h>
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#include <sys/unistd.h>
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#include <sys/callout.h>
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#include <sys/malloc.h>
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#include <sys/priv.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usb_core.h>
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#include <dev/usb/usb_busdma.h>
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#include <dev/usb/usb_process.h>
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#include <dev/usb/usb_util.h>
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#include <dev/usb/usb_controller.h>
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#include <dev/usb/usb_bus.h>
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#include <dev/usb/controller/ehci.h>
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#include <dev/usb/controller/ehcireg.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#define EHCI_VENDORID_MRVL 0x1286
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#define EHCI_HC_DEVSTR "Marvell Integrated USB 2.0 controller"
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static device_attach_t mv_ehci_attach;
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static device_detach_t mv_ehci_detach;
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static int err_intr(void *arg);
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static struct resource *irq_err;
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static void *ih_err;
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/* EHCI HC regs start at this offset within USB range */
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#define MV_USB_HOST_OFST 0x0100
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#define USB_BRIDGE_INTR_CAUSE 0x210
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#define USB_BRIDGE_INTR_MASK 0x214
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#define USB_BRIDGE_ERR_ADDR 0x21C
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#define MV_USB_ADDR_DECODE_ERR (1 << 0)
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#define MV_USB_HOST_UNDERFLOW (1 << 1)
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#define MV_USB_HOST_OVERFLOW (1 << 2)
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#define MV_USB_DEVICE_UNDERFLOW (1 << 3)
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static struct ofw_compat_data compat_data[] = {
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{"mrvl,usb-ehci", true},
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{"marvell,orion-ehci", true},
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{NULL, false}
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};
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static void
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mv_ehci_post_reset(struct ehci_softc *ehci_softc)
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{
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uint32_t usbmode;
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/* Force HOST mode */
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usbmode = EOREAD4(ehci_softc, EHCI_USBMODE_NOLPM);
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usbmode &= ~EHCI_UM_CM;
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usbmode |= EHCI_UM_CM_HOST;
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EOWRITE4(ehci_softc, EHCI_USBMODE_NOLPM, usbmode);
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}
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static int
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mv_ehci_probe(device_t self)
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{
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if (!ofw_bus_status_okay(self))
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return (ENXIO);
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if (!ofw_bus_search_compatible(self, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(self, EHCI_HC_DEVSTR);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mv_ehci_attach(device_t self)
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{
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ehci_softc_t *sc = device_get_softc(self);
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bus_space_handle_t bsh;
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int err;
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int rid;
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/* initialise some bus fields */
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sc->sc_bus.parent = self;
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sc->sc_bus.devices = sc->sc_devices;
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sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
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sc->sc_bus.dma_bits = 32;
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/* get all DMA memory */
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if (usb_bus_mem_alloc_all(&sc->sc_bus,
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USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
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return (ENOMEM);
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}
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rid = 0;
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sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (!sc->sc_io_res) {
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device_printf(self, "Could not map memory\n");
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goto error;
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}
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sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
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bsh = rman_get_bushandle(sc->sc_io_res);
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sc->sc_io_size = rman_get_size(sc->sc_io_res) - MV_USB_HOST_OFST;
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/*
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* Marvell EHCI host controller registers start at certain offset
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* within the whole USB registers range, so create a subregion for the
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* host mode configuration purposes.
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*/
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if (bus_space_subregion(sc->sc_io_tag, bsh, MV_USB_HOST_OFST,
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sc->sc_io_size, &sc->sc_io_hdl) != 0)
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panic("%s: unable to subregion USB host registers",
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device_get_name(self));
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rid = 0;
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if (!ofw_bus_is_compatible(self, "marvell,orion-ehci")) {
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irq_err = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (irq_err == NULL) {
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device_printf(self, "Could not allocate error irq\n");
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mv_ehci_detach(self);
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return (ENXIO);
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}
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rid = 1;
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}
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/*
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* Notice: Marvell EHCI controller has TWO interrupt lines, so make
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* sure to use the correct rid for the main one (controller interrupt)
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* -- refer to DTS for the right resource number to use here.
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*/
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sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->sc_irq_res == NULL) {
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device_printf(self, "Could not allocate irq\n");
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goto error;
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}
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sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
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if (!sc->sc_bus.bdev) {
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device_printf(self, "Could not add USB device\n");
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goto error;
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}
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device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
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device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
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sprintf(sc->sc_vendor, "Marvell");
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if (!ofw_bus_is_compatible(self, "marvell,orion-ehci")) {
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err = bus_setup_intr(self, irq_err, INTR_TYPE_BIO,
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err_intr, NULL, sc, &ih_err);
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if (err) {
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device_printf(self, "Could not setup error irq, %d\n", err);
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ih_err = NULL;
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goto error;
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}
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}
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EWRITE4(sc, USB_BRIDGE_INTR_MASK, MV_USB_ADDR_DECODE_ERR |
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MV_USB_HOST_UNDERFLOW | MV_USB_HOST_OVERFLOW |
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MV_USB_DEVICE_UNDERFLOW);
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err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
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if (err) {
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device_printf(self, "Could not setup irq, %d\n", err);
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sc->sc_intr_hdl = NULL;
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goto error;
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}
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/*
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* Workaround for Marvell integrated EHCI controller: reset of
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* the EHCI core clears the USBMODE register, which sets the core in
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* an undefined state (neither host nor agent), so it needs to be set
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* again for proper operation.
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*
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* Refer to errata document MV-S500832-00D.pdf (p. 5.24 GL USB-2) for
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* details.
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*/
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sc->sc_vendor_post_reset = mv_ehci_post_reset;
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if (bootverbose)
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device_printf(self, "5.24 GL USB-2 workaround enabled\n");
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/* XXX all MV chips need it? */
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sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
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sc->sc_vendor_get_port_speed = ehci_get_port_speed_portsc;
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err = ehci_init(sc);
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if (!err) {
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err = device_probe_and_attach(sc->sc_bus.bdev);
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}
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if (err) {
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device_printf(self, "USB init failed err=%d\n", err);
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goto error;
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}
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return (0);
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error:
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mv_ehci_detach(self);
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return (ENXIO);
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}
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static int
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mv_ehci_detach(device_t self)
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{
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ehci_softc_t *sc = device_get_softc(self);
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device_t bdev;
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int err;
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if (sc->sc_bus.bdev) {
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bdev = sc->sc_bus.bdev;
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device_detach(bdev);
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device_delete_child(self, bdev);
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}
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/* during module unload there are lots of children leftover */
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device_delete_children(self);
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/*
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* disable interrupts that might have been switched on in mv_ehci_attach
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*/
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if (sc->sc_io_res) {
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EWRITE4(sc, USB_BRIDGE_INTR_MASK, 0);
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}
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if (sc->sc_irq_res && sc->sc_intr_hdl) {
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/*
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* only call ehci_detach() after ehci_init()
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*/
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ehci_detach(sc);
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err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
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if (err)
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/* XXX or should we panic? */
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device_printf(self, "Could not tear down irq, %d\n",
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err);
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sc->sc_intr_hdl = NULL;
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}
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if (irq_err && ih_err) {
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err = bus_teardown_intr(self, irq_err, ih_err);
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if (err)
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device_printf(self, "Could not tear down irq, %d\n",
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err);
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ih_err = NULL;
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}
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if (irq_err) {
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bus_release_resource(self, SYS_RES_IRQ, 0, irq_err);
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irq_err = NULL;
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}
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if (sc->sc_irq_res) {
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bus_release_resource(self, SYS_RES_IRQ, 1, sc->sc_irq_res);
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sc->sc_irq_res = NULL;
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}
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if (sc->sc_io_res) {
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bus_release_resource(self, SYS_RES_MEMORY, 0,
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sc->sc_io_res);
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sc->sc_io_res = NULL;
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}
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usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
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return (0);
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}
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static int
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err_intr(void *arg)
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{
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ehci_softc_t *sc = arg;
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unsigned int cause;
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cause = EREAD4(sc, USB_BRIDGE_INTR_CAUSE);
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if (cause) {
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printf("USB error: ");
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if (cause & MV_USB_ADDR_DECODE_ERR) {
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uint32_t addr;
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addr = EREAD4(sc, USB_BRIDGE_ERR_ADDR);
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printf("address decoding error (addr=%#x)\n", addr);
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}
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if (cause & MV_USB_HOST_UNDERFLOW)
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printf("host underflow\n");
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if (cause & MV_USB_HOST_OVERFLOW)
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printf("host overflow\n");
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if (cause & MV_USB_DEVICE_UNDERFLOW)
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printf("device underflow\n");
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if (cause & ~(MV_USB_ADDR_DECODE_ERR | MV_USB_HOST_UNDERFLOW |
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MV_USB_HOST_OVERFLOW | MV_USB_DEVICE_UNDERFLOW))
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printf("unknown cause (cause=%#x)\n", cause);
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EWRITE4(sc, USB_BRIDGE_INTR_CAUSE, 0);
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}
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return (FILTER_HANDLED);
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}
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static device_method_t ehci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mv_ehci_probe),
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DEVMETHOD(device_attach, mv_ehci_attach),
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DEVMETHOD(device_detach, mv_ehci_detach),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t ehci_driver = {
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"ehci",
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ehci_methods,
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sizeof(ehci_softc_t),
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};
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static devclass_t ehci_devclass;
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DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0);
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MODULE_DEPEND(ehci, usb, 1, 1, 1);
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