Marcel Moolenaar e4f72b32cb o When not making a translation cache-inhibit and guarded (PTE_I|PTE_G) ... make it memory-coherency enforced (PTE_M). This is required for SMP to work. o Serialize tlbie operations and implement the tlbie operation in a function called tlbie(). Hardware can end up in a live-lock if between the tlbsync and subsequent sync on one processor another processor executes a tlbie or tlbsync. o Eliminate the following defines: TLBIE, TLBSYNC, SYNC and EIEIO Use either inline assembly statements or inline functions defined in <machine/cpufunc.h>		2008-09-16 19:16:33 +00:00
..
clock.c	o In decr_get_timecount() only read the low timebase register.	2008-09-16 17:11:33 +00:00
copyinout.c	Fix remaining compile error.	2006-10-18 19:56:20 +00:00
interrupt.c	Trace interrupts with KTR_INTR.	2008-08-31 23:54:22 +00:00
locore.S	MFp4: SMP support	2008-04-27 22:33:43 +00:00
machdep.c	Call powerpc_sync() instead of using an asm statement.	2008-08-30 18:39:29 +00:00
mmu_oea.c	o When not making a translation cache-inhibit and guarded (PTE_I|PTE_G)	2008-09-16 19:16:33 +00:00
mp_cpudep.c	Rewrite cpudep_ap_bootstrap(). We now enable L3, L2, L1D and L1I	2008-09-16 17:22:16 +00:00
nexus.c	Switch to using genclock. Have nexus double as clock device for	2008-04-21 04:41:37 +00:00
ofw_machdep.c	Remove SMP left-overs from NetBSD.	2008-02-12 20:55:51 +00:00
ofwmagic.S
swtch.S	Set pcpup->pc_curthread and pcpup->pc_curpcb before calling	2008-09-16 17:03:52 +00:00
trap_subr.S	Remove the tracing from the AP startup. The AP is known	2008-09-16 01:05:54 +00:00
trap.c	Add link register to fatal trap printout to better diagnose NULL	2008-06-04 07:32:49 +00:00
uio_machdep.c	Add kdb_cpu_sync_icache(), intended to synchronize instruction	2007-06-09 21:55:17 +00:00
uma_machdep.c	It has been observed on the mailing lists that the different categories	2007-09-15 18:47:02 +00:00
vm_machdep.c	Whitespace fixes.	2008-08-30 18:48:17 +00:00