e53470fee3
- Support for Texas Instruments SoCs: - AM335x - OMAP4 - Kernel configs, DTS for Beaglebone and Pandaboard Submitted by: Ben Gray, Damjan Marion
125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
/*-
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_CPSWVAR_H
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#define _IF_CPSWVAR_H
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#define CPSW_INTR_COUNT 4
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/* MII BUS */
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#define CPSW_MIIBUS_RETRIES 5
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#define CPSW_MIIBUS_DELAY 1000
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#define CPSW_MAX_TX_BUFFERS 128
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#define CPSW_MAX_RX_BUFFERS 128
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#define CPSW_MAX_ALE_ENTRIES 1024
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struct cpsw_softc {
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struct ifnet *ifp;
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phandle_t node;
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device_t dev;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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device_t miibus;
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struct mii_data *mii;
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struct mtx tx_lock; /* transmitter lock */
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struct mtx rx_lock; /* receiver lock */
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struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */
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void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */
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uint32_t cpsw_if_flags;
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int cpsw_media_status;
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struct callout wd_callout;
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int wd_timer;
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/* buffers */
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bus_dma_tag_t mbuf_dtag;
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bus_dmamap_t tx_dmamap[CPSW_MAX_TX_BUFFERS];
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bus_dmamap_t rx_dmamap[CPSW_MAX_RX_BUFFERS];
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struct mbuf *tx_mbuf[CPSW_MAX_TX_BUFFERS];
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struct mbuf *rx_mbuf[CPSW_MAX_RX_BUFFERS];
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int txbd_head;
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int txbd_queue_size;
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int rxbd_head;
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int rxbd_tail;
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int tmp;
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int eoq;
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int tc[CPSW_MAX_TX_BUFFERS];
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int tc_unload[CPSW_MAX_TX_BUFFERS];
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struct cpsw_softc *phy_sc;
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};
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#define CPDMA_BD_SOP (1<<15)
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#define CPDMA_BD_EOP (1<<14)
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#define CPDMA_BD_OWNER (1<<13)
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#define CPDMA_BD_EOQ (1<<12)
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#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
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struct cpsw_cpdma_bd {
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volatile uint32_t next;
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volatile uint32_t bufptr;
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volatile uint16_t buflen;
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volatile uint16_t bufoff;
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volatile uint16_t pktlen;
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volatile uint16_t flags;
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};
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/* Read/Write macros */
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#define cpsw_read_4(reg) bus_read_4(sc->res[0], reg)
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#define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val)
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#define cpsw_cpdma_txbd_offset(i) \
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(CPSW_CPPI_RAM_OFFSET + ((i)*16))
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#define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \
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vtophys(rman_get_start(sc->res[0])))
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#define cpsw_cpdma_read_txbd(i, val) \
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bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_txbd(i, val) \
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bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_txbd_next(i, val) \
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bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val)
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#define cpsw_cpdma_read_txbd_flags(i) \
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bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14)
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#define cpsw_cpdma_rxbd_offset(i) \
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(CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16))
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#define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \
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vtophys(rman_get_start(sc->res[0])))
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#define cpsw_cpdma_read_rxbd(i, val) \
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bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_rxbd(i, val) \
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bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_rxbd_next(i, val) \
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bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val)
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#define cpsw_cpdma_read_rxbd_flags(i) \
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bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14)
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#endif /*_IF_CPSWVAR_H */
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