e5db313494
Restore the SIMD optimization for 4.19.38 LTS, 4.14.120 LTS,
and 5.0 and newer kernels. This is accomplished by leveraging
the fact that by definition dedicated kernel threads never need
to concern themselves with saving and restoring the user FPU state.
Therefore, they may use the FPU as long as we can guarantee user
tasks always restore their FPU state before context switching back
to user space.
For the 5.0 and 5.1 kernels disabling preemption and local
interrupts is sufficient to allow the FPU to be used. All non-kernel
threads will restore the preserved user FPU state.
For 5.2 and latter kernels the user FPU state restoration will be
skipped if the kernel determines the registers have not changed.
Therefore, for these kernels we need to perform the additional
step of saving and restoring the FPU registers. Invalidating the
per-cpu global tracking the FPU state would force a restore but
that functionality is private to the core x86 FPU implementation
and unavailable.
In practice, restricting SIMD to kernel threads is not a major
restriction for ZFS. The vast majority of SIMD operations are
already performed by the IO pipeline. The remaining cases are
relatively infrequent and can be handled by the generic code
without significant impact. The two most noteworthy cases are:
1) Decrypting the wrapping key for an encrypted dataset,
i.e. `zfs load-key`. All other encryption and decryption
operations will use the SIMD optimized implementations.
2) Generating the payload checksums for a `zfs send` stream.
In order to avoid making any changes to the higher layers of ZFS
all of the `*_get_ops()` functions were updated to take in to
consideration the calling context. This allows for the fastest
implementation to be used as appropriate (see kfpu_allowed()).
The only other notable instance of SIMD operations being used
outside a kernel thread was at module load time. This code
was moved in to a taskq in order to accommodate the new kernel
thread restriction.
Finally, a few other modifications were made in order to further
harden this code and facilitate testing. They include updating
each implementations operations structure to be declared as a
constant. And allowing "cycle" to be set when selecting the
preferred ops in the kernel as well as user space.
Reviewed-by: Tony Hutter <hutter2@llnl.gov>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Closes #8754
Closes #8793
Closes #8965
175 lines
5.1 KiB
C
175 lines
5.1 KiB
C
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Gvozden Nešković. All rights reserved.
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*/
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#if defined(__x86_64) && defined(HAVE_AVX512F)
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#include <linux/simd_x86.h>
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#include <sys/byteorder.h>
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#include <sys/frame.h>
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#include <sys/spa_checksum.h>
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#include <sys/strings.h>
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#include <zfs_fletcher.h>
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#define __asm __asm__ __volatile__
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static void
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fletcher_4_avx512f_init(fletcher_4_ctx_t *ctx)
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{
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bzero(ctx->avx512, 4 * sizeof (zfs_fletcher_avx512_t));
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}
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static void
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fletcher_4_avx512f_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
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{
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static const uint64_t
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CcA[] = { 0, 0, 1, 3, 6, 10, 15, 21 },
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CcB[] = { 28, 36, 44, 52, 60, 68, 76, 84 },
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DcA[] = { 0, 0, 0, 1, 4, 10, 20, 35 },
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DcB[] = { 56, 84, 120, 164, 216, 276, 344, 420 },
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DcC[] = { 448, 512, 576, 640, 704, 768, 832, 896 };
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uint64_t A, B, C, D;
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uint64_t i;
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A = ctx->avx512[0].v[0];
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B = 8 * ctx->avx512[1].v[0];
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C = 64 * ctx->avx512[2].v[0] - CcB[0] * ctx->avx512[1].v[0];
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D = 512 * ctx->avx512[3].v[0] - DcC[0] * ctx->avx512[2].v[0] +
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DcB[0] * ctx->avx512[1].v[0];
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for (i = 1; i < 8; i++) {
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A += ctx->avx512[0].v[i];
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B += 8 * ctx->avx512[1].v[i] - i * ctx->avx512[0].v[i];
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C += 64 * ctx->avx512[2].v[i] - CcB[i] * ctx->avx512[1].v[i] +
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CcA[i] * ctx->avx512[0].v[i];
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D += 512 * ctx->avx512[3].v[i] - DcC[i] * ctx->avx512[2].v[i] +
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DcB[i] * ctx->avx512[1].v[i] - DcA[i] * ctx->avx512[0].v[i];
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}
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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#define FLETCHER_4_AVX512_RESTORE_CTX(ctx) \
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{ \
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__asm("vmovdqu64 %0, %%zmm0" :: "m" ((ctx)->avx512[0])); \
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__asm("vmovdqu64 %0, %%zmm1" :: "m" ((ctx)->avx512[1])); \
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__asm("vmovdqu64 %0, %%zmm2" :: "m" ((ctx)->avx512[2])); \
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__asm("vmovdqu64 %0, %%zmm3" :: "m" ((ctx)->avx512[3])); \
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}
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#define FLETCHER_4_AVX512_SAVE_CTX(ctx) \
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{ \
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__asm("vmovdqu64 %%zmm0, %0" : "=m" ((ctx)->avx512[0])); \
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__asm("vmovdqu64 %%zmm1, %0" : "=m" ((ctx)->avx512[1])); \
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__asm("vmovdqu64 %%zmm2, %0" : "=m" ((ctx)->avx512[2])); \
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__asm("vmovdqu64 %%zmm3, %0" : "=m" ((ctx)->avx512[3])); \
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}
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static void
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fletcher_4_avx512f_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
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{
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const uint32_t *ip = buf;
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const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_AVX512_RESTORE_CTX(ctx);
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for (; ip < ipend; ip += 8) {
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__asm("vpmovzxdq %0, %%zmm4"::"m" (*ip));
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__asm("vpaddq %zmm4, %zmm0, %zmm0");
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__asm("vpaddq %zmm0, %zmm1, %zmm1");
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__asm("vpaddq %zmm1, %zmm2, %zmm2");
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__asm("vpaddq %zmm2, %zmm3, %zmm3");
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}
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FLETCHER_4_AVX512_SAVE_CTX(ctx);
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kfpu_end();
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}
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STACK_FRAME_NON_STANDARD(fletcher_4_avx512f_native);
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static void
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fletcher_4_avx512f_byteswap(fletcher_4_ctx_t *ctx, const void *buf,
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uint64_t size)
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{
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static const uint64_t byteswap_mask = 0xFFULL;
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const uint32_t *ip = buf;
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const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_AVX512_RESTORE_CTX(ctx);
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__asm("vpbroadcastq %0, %%zmm8" :: "r" (byteswap_mask));
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__asm("vpsllq $8, %zmm8, %zmm9");
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__asm("vpsllq $16, %zmm8, %zmm10");
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__asm("vpsllq $24, %zmm8, %zmm11");
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for (; ip < ipend; ip += 8) {
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__asm("vpmovzxdq %0, %%zmm5"::"m" (*ip));
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__asm("vpsrlq $24, %zmm5, %zmm6");
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__asm("vpandd %zmm8, %zmm6, %zmm6");
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__asm("vpsrlq $8, %zmm5, %zmm7");
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__asm("vpandd %zmm9, %zmm7, %zmm7");
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__asm("vpord %zmm6, %zmm7, %zmm4");
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__asm("vpsllq $8, %zmm5, %zmm6");
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__asm("vpandd %zmm10, %zmm6, %zmm6");
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__asm("vpord %zmm6, %zmm4, %zmm4");
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__asm("vpsllq $24, %zmm5, %zmm5");
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__asm("vpandd %zmm11, %zmm5, %zmm5");
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__asm("vpord %zmm5, %zmm4, %zmm4");
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__asm("vpaddq %zmm4, %zmm0, %zmm0");
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__asm("vpaddq %zmm0, %zmm1, %zmm1");
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__asm("vpaddq %zmm1, %zmm2, %zmm2");
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__asm("vpaddq %zmm2, %zmm3, %zmm3");
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}
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FLETCHER_4_AVX512_SAVE_CTX(ctx)
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kfpu_end();
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}
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STACK_FRAME_NON_STANDARD(fletcher_4_avx512f_byteswap);
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static boolean_t
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fletcher_4_avx512f_valid(void)
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{
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return (kfpu_allowed() && zfs_avx512f_available());
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}
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const fletcher_4_ops_t fletcher_4_avx512f_ops = {
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.init_native = fletcher_4_avx512f_init,
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.fini_native = fletcher_4_avx512f_fini,
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.compute_native = fletcher_4_avx512f_native,
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.init_byteswap = fletcher_4_avx512f_init,
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.fini_byteswap = fletcher_4_avx512f_fini,
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.compute_byteswap = fletcher_4_avx512f_byteswap,
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.valid = fletcher_4_avx512f_valid,
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.name = "avx512f"
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};
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#endif /* defined(__x86_64) && defined(HAVE_AVX512F) */
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