04dda605c5
various pcib drivers to use their own private devclass_t variables for their modules. - Use the DEFINE_CLASS_0() macro to declare drivers for the various pcib drivers while I'm here.
381 lines
10 KiB
C
381 lines
10 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <isa/isavar.h>
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#include <machine/legacyvar.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/resource.h>
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#include "pcib_if.h"
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int
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legacy_pcib_maxslots(device_t dev)
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{
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return 31;
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}
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/* read configuration space register */
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u_int32_t
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legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
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int reg, int bytes)
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{
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return(pci_cfgregread(bus, slot, func, reg, bytes));
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}
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/* write configuration space register */
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void
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legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
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int reg, u_int32_t data, int bytes)
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{
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pci_cfgregwrite(bus, slot, func, reg, data, bytes);
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}
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/* route interrupt */
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static int
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legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
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{
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/* No routing possible */
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return (PCI_INVALID_IRQ);
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}
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static const char *
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legacy_pcib_is_host_bridge(int bus, int slot, int func,
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uint32_t id, uint8_t class, uint8_t subclass,
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uint8_t *busnum)
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{
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const char *s = NULL;
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*busnum = 0;
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if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
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s = "Host to PCI bridge";
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return s;
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}
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/*
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* Scan the first pci bus for host-pci bridges and add pcib instances
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* to the nexus for each bridge.
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*/
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static void
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legacy_pcib_identify(driver_t *driver, device_t parent)
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{
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int bus, slot, func;
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u_int8_t hdrtype;
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int found = 0;
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int pcifunchigh;
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int found824xx = 0;
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int found_orion = 0;
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device_t child;
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devclass_t pci_devclass;
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if (pci_cfgregopen() == 0)
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return;
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/*
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* Check to see if we haven't already had a PCI bus added
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* via some other means. If we have, bail since otherwise
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* we're going to end up duplicating it.
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*/
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if ((pci_devclass = devclass_find("pci")) &&
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devclass_get_device(pci_devclass, 0))
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return;
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bus = 0;
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retry:
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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func = 0;
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hdrtype = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_HDRTYPE, 1);
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/*
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* When enumerating bus devices, the standard says that
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* one should check the header type and ignore the slots whose
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* header types that the software doesn't know about. We use
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* this to filter out devices.
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*/
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if ((hdrtype & PCIM_MFDEV) &&
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(!found_orion || hdrtype != 0xff))
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pcifunchigh = PCI_FUNCMAX;
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else
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pcifunchigh = 0;
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for (func = 0; func <= pcifunchigh; func++) {
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/*
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* Read the IDs and class from the device.
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*/
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u_int32_t id;
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u_int8_t class, subclass, busnum;
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const char *s;
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device_t *devs;
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int ndevs, i;
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id = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_DEVVENDOR, 4);
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if (id == -1)
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continue;
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class = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_CLASS, 1);
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subclass = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_SUBCLASS, 1);
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s = legacy_pcib_is_host_bridge(bus, slot, func,
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id, class, subclass,
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&busnum);
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if (s == NULL)
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continue;
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/*
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* Check to see if the physical bus has already
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* been seen. Eg: hybrid 32 and 64 bit host
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* bridges to the same logical bus.
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*/
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if (device_get_children(parent, &devs, &ndevs) == 0) {
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for (i = 0; s != NULL && i < ndevs; i++) {
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if (strcmp(device_get_name(devs[i]),
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"pcib") != 0)
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continue;
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if (legacy_get_pcibus(devs[i]) == busnum)
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s = NULL;
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}
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free(devs, M_TEMP);
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}
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if (s == NULL)
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continue;
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/*
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* Add at priority 100 to make sure we
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* go after any motherboard resources
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*/
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child = BUS_ADD_CHILD(parent, 100,
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"pcib", busnum);
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device_set_desc(child, s);
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legacy_set_pcibus(child, busnum);
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found = 1;
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if (id == 0x12258086)
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found824xx = 1;
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if (id == 0x84c48086)
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found_orion = 1;
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}
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}
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if (found824xx && bus == 0) {
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bus++;
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goto retry;
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}
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/*
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* Make sure we add at least one bridge since some old
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* hardware doesn't actually have a host-pci bridge device.
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* Note that pci_cfgregopen() thinks we have PCI devices..
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*/
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if (!found) {
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if (bootverbose)
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printf(
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"legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
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child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
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legacy_set_pcibus(child, 0);
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}
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}
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static int
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legacy_pcib_probe(device_t dev)
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{
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if (pci_cfgregopen() == 0)
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return ENXIO;
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return -100;
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}
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static int
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legacy_pcib_attach(device_t dev)
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{
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int bus;
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bus = pcib_get_bus(dev);
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device_add_child(dev, "pci", bus);
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return bus_generic_attach(dev);
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}
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int
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legacy_pcib_read_ivar(device_t dev, device_t child, int which,
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uintptr_t *result)
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{
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = legacy_get_pcibus(dev);
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return 0;
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}
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return ENOENT;
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}
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int
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legacy_pcib_write_ivar(device_t dev, device_t child, int which,
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uintptr_t value)
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{
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switch (which) {
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case PCIB_IVAR_BUS:
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legacy_set_pcibus(dev, value);
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return 0;
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}
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return ENOENT;
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}
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SYSCTL_DECL(_hw_pci);
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static unsigned long legacy_host_mem_start = 0x80000000;
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TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
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SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
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&legacy_host_mem_start, 0x80000000,
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"Limit the host bridge memory to being above this address. Must be\n\
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set at boot via a tunable.");
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struct resource *
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legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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/*
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* If no memory preference is given, use upper 32MB slot most
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* bioses use for their memory window. Typically other bridges
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* before us get in the way to assert their preferences on memory.
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* Hardcoding like this sucks, so a more MD/MI way needs to be
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* found to do it. This is typically only used on older laptops
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* that don't have pci busses behind pci bridge, so assuming > 32MB
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* is liekly OK.
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*
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* However, this can cause problems for other chipsets, so we make
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* this tunable by hw.pci.host_mem_start.
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*/
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if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
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start = legacy_host_mem_start;
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if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
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start = 0x1000;
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return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
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count, flags));
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}
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static device_method_t legacy_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, legacy_pcib_identify),
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DEVMETHOD(device_probe, legacy_pcib_probe),
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DEVMETHOD(device_attach, legacy_pcib_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
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DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
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DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
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{ 0, 0 }
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};
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static devclass_t pcib_devclass;
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DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
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DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, pcib_devclass, 0, 0);
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/*
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* Install placeholder to claim the resources owned by the
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* PCI bus interface. This could be used to extract the
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* config space registers in the extreme case where the PnP
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* ID is available and the PCI BIOS isn't, but for now we just
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* eat the PnP ID and do nothing else.
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*
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* XXX we should silence this probe, as it will generally confuse
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* people.
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*/
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static struct isa_pnp_id pcibus_pnp_ids[] = {
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{ 0x030ad041 /* PNP0A03 */, "PCI Bus" },
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{ 0 }
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};
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static int
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pcibus_pnp_probe(device_t dev)
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{
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int result;
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if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
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device_quiet(dev);
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return(result);
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}
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static int
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pcibus_pnp_attach(device_t dev)
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{
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return(0);
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}
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static device_method_t pcibus_pnp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pcibus_pnp_probe),
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DEVMETHOD(device_attach, pcibus_pnp_attach),
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DEVMETHOD(device_detach, bus_generic_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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{ 0, 0 }
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};
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static devclass_t pcibus_pnp_devclass;
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DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
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DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
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