26b9f0eb98
The interrupts-extended property is a list of controller-specific interrupt tuples for more than one controller. The decode routine of every PIC gets called in the pre-INTRNG code (nexus doesn't know which device instance belongs to which fdt node), so the GIC code has to check each FDT node it is asked to decode to ensure it is the owner. Because in the pre-INTRNG world there can only be one instance of a GIC, it's safe to cache the results of a positive lookup in a static variable to avoid the expensive lookups on subsequent calls. Submitted by: Svatopluk Kraus <onwahe@gmail.com> Differential Revision: https://reviews.freebsd.org/D2345
193 lines
5.8 KiB
C
193 lines
5.8 KiB
C
/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */
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/*-
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* Copyright (c) 1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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#ifdef FDT
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#include <dev/ofw/openfirm.h>
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#endif
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#ifdef ARM_INTRNG
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#ifndef NIRQ
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#define NIRQ 1024 /* XXX - It should be an option. */
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#endif
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#ifdef notyet
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#define INTR_SOLO INTR_MD1
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typedef int arm_irq_filter_t(void *arg, struct trapframe *tf);
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#else
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typedef int arm_irq_filter_t(void *arg);
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#endif
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#define ARM_ISRC_NAMELEN (MAXCOMLEN + 1)
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typedef void arm_ipi_filter_t(void *arg);
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enum arm_isrc_type {
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ARM_ISRCT_NAMESPACE,
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ARM_ISRCT_FDT
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};
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#define ARM_ISRCF_REGISTERED 0x01 /* registered in a controller */
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#define ARM_ISRCF_PERCPU 0x02 /* per CPU interrupt */
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#define ARM_ISRCF_BOUND 0x04 /* bound to a CPU */
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/* Interrupt source definition. */
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struct arm_irqsrc {
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device_t isrc_dev; /* where isrc is mapped */
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intptr_t isrc_xref; /* device reference key */
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uintptr_t isrc_data; /* device data for isrc */
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u_int isrc_irq; /* unique identificator */
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enum arm_isrc_type isrc_type; /* how is isrc decribed */
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u_int isrc_flags;
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char isrc_name[ARM_ISRC_NAMELEN];
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uint16_t isrc_nspc_type;
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uint16_t isrc_nspc_num;
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enum intr_trigger isrc_trig;
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enum intr_polarity isrc_pol;
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cpuset_t isrc_cpu; /* on which CPUs is enabled */
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u_int isrc_index;
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u_long * isrc_count;
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u_int isrc_handlers;
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struct intr_event * isrc_event;
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arm_irq_filter_t * isrc_filter;
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arm_ipi_filter_t * isrc_ipifilter;
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void * isrc_arg;
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#ifdef FDT
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u_int isrc_ncells;
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pcell_t isrc_cells[]; /* leave it last */
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#endif
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};
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void arm_irq_set_name(struct arm_irqsrc *isrc, const char *fmt, ...)
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__printflike(2, 3);
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void arm_irq_dispatch(struct arm_irqsrc *isrc, struct trapframe *tf);
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#define ARM_IRQ_NSPC_NONE 0
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#define ARM_IRQ_NSPC_PLAIN 1
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#define ARM_IRQ_NSPC_IRQ 2
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#define ARM_IRQ_NSPC_IPI 3
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u_int arm_namespace_map_irq(device_t dev, uint16_t type, uint16_t num);
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#ifdef FDT
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u_int arm_fdt_map_irq(phandle_t, pcell_t *, u_int);
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#endif
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int arm_pic_register(device_t dev, intptr_t xref);
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int arm_pic_unregister(device_t dev, intptr_t xref);
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int arm_pic_claim_root(device_t dev, intptr_t xref, arm_irq_filter_t *filter,
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void *arg, u_int ipicount);
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int arm_irq_add_handler(device_t dev, driver_filter_t, driver_intr_t, void *,
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u_int, int, void **);
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int arm_irq_remove_handler(device_t dev, u_int, void *);
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int arm_irq_config(u_int, enum intr_trigger, enum intr_polarity);
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int arm_irq_describe(u_int, void *, const char *);
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u_int arm_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask);
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#ifdef SMP
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int arm_irq_bind(u_int, int);
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void arm_ipi_dispatch(struct arm_irqsrc *isrc, struct trapframe *tf);
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#define AISHF_NOALLOC 0x0001
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int arm_ipi_set_handler(u_int ipi, const char *name, arm_ipi_filter_t *filter,
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void *arg, u_int flags);
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void arm_pic_init_secondary(void);
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#endif
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#else /* ARM_INTRNG */
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/* XXX move to std.* files? */
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#ifdef CPU_XSCALE_81342
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#define NIRQ 128
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#elif defined(CPU_XSCALE_PXA2X0)
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#include <arm/xscale/pxa/pxareg.h>
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#define NIRQ IRQ_GPIO_MAX
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#elif defined(SOC_MV_DISCOVERY)
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#define NIRQ 96
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#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \
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defined(CPU_XSCALE_IXP435)
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#define NIRQ 64
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#elif defined(CPU_CORTEXA)
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#define NIRQ 1020
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#elif defined(CPU_KRAIT)
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#define NIRQ 288
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#elif defined(CPU_ARM1176)
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#define NIRQ 128
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#elif defined(SOC_MV_ARMADAXP)
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#define MAIN_IRQ_NUM 116
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#define ERR_IRQ_NUM 32
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#define ERR_IRQ (MAIN_IRQ_NUM)
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#define MSI_IRQ_NUM 32
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#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
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#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM)
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#else
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#define NIRQ 32
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#endif
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int arm_get_next_irq(int);
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void arm_mask_irq(uintptr_t);
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void arm_unmask_irq(uintptr_t);
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void arm_intrnames_init(void);
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void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*),
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void *, int, int, void **);
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int arm_remove_irqhandler(int, void *);
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extern void (*arm_post_filter)(void *);
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extern int (*arm_config_irq)(int irq, enum intr_trigger trig,
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enum intr_polarity pol);
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void arm_pic_init_secondary(void);
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#ifdef FDT
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int gic_decode_fdt(phandle_t, pcell_t *, int *, int *, int *);
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int arm_fdt_map_irq(phandle_t, pcell_t *, int);
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#endif
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#endif /* ARM_INTRNG */
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void arm_irq_memory_barrier(uintptr_t);
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#endif /* _MACHINE_INTR_H */
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