1de7b4b805
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. No functional change intended.
935 lines
22 KiB
C
935 lines
22 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#ifndef WITHOUT_CAPSICUM
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#include <sys/capsicum.h>
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#endif
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <sys/pciio.h>
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#include <sys/ioctl.h>
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#include <dev/io/iodev.h>
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#include <dev/pci/pcireg.h>
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#include <machine/iodev.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <sysexits.h>
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#include <unistd.h>
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#include <machine/vmm.h>
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#include <vmmapi.h>
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#include "pci_emul.h"
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#include "mem.h"
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#ifndef _PATH_DEVPCI
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#define _PATH_DEVPCI "/dev/pci"
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#endif
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#ifndef _PATH_DEVIO
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#define _PATH_DEVIO "/dev/io"
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#endif
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#ifndef _PATH_MEM
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#define _PATH_MEM "/dev/mem"
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#endif
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#define LEGACY_SUPPORT 1
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#define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
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#define MSIX_CAPLEN 12
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static int pcifd = -1;
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static int iofd = -1;
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static int memfd = -1;
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struct passthru_softc {
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struct pci_devinst *psc_pi;
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struct pcibar psc_bar[PCI_BARMAX + 1];
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struct {
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int capoff;
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int msgctrl;
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int emulated;
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} psc_msi;
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struct {
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int capoff;
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} psc_msix;
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struct pcisel psc_sel;
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};
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static int
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msi_caplen(int msgctrl)
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{
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int len;
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len = 10; /* minimum length of msi capability */
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if (msgctrl & PCIM_MSICTRL_64BIT)
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len += 4;
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#if 0
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/*
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* Ignore the 'mask' and 'pending' bits in the MSI capability.
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* We'll let the guest manipulate them directly.
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*/
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if (msgctrl & PCIM_MSICTRL_VECTOR)
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len += 10;
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#endif
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return (len);
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}
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static uint32_t
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read_config(const struct pcisel *sel, long reg, int width)
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{
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struct pci_io pi;
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bzero(&pi, sizeof(pi));
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pi.pi_sel = *sel;
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pi.pi_reg = reg;
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pi.pi_width = width;
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if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
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return (0); /* XXX */
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else
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return (pi.pi_data);
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}
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static void
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write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
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{
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struct pci_io pi;
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bzero(&pi, sizeof(pi));
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pi.pi_sel = *sel;
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pi.pi_reg = reg;
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pi.pi_width = width;
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pi.pi_data = data;
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(void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
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}
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#ifdef LEGACY_SUPPORT
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static int
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passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
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{
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int capoff, i;
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struct msicap msicap;
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u_char *capdata;
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pci_populate_msicap(&msicap, msgnum, nextptr);
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/*
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* XXX
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* Copy the msi capability structure in the last 16 bytes of the
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* config space. This is wrong because it could shadow something
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* useful to the device.
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*/
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capoff = 256 - roundup(sizeof(msicap), 4);
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capdata = (u_char *)&msicap;
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for (i = 0; i < sizeof(msicap); i++)
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pci_set_cfgdata8(pi, capoff + i, capdata[i]);
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return (capoff);
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}
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#endif /* LEGACY_SUPPORT */
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static int
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cfginitmsi(struct passthru_softc *sc)
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{
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int i, ptr, capptr, cap, sts, caplen, table_size;
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uint32_t u32;
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struct pcisel sel;
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struct pci_devinst *pi;
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struct msixcap msixcap;
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uint32_t *msixcap_ptr;
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pi = sc->psc_pi;
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sel = sc->psc_sel;
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/*
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* Parse the capabilities and cache the location of the MSI
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* and MSI-X capabilities.
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*/
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sts = read_config(&sel, PCIR_STATUS, 2);
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if (sts & PCIM_STATUS_CAPPRESENT) {
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ptr = read_config(&sel, PCIR_CAP_PTR, 1);
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while (ptr != 0 && ptr != 0xff) {
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cap = read_config(&sel, ptr + PCICAP_ID, 1);
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if (cap == PCIY_MSI) {
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/*
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* Copy the MSI capability into the config
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* space of the emulated pci device
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*/
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sc->psc_msi.capoff = ptr;
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sc->psc_msi.msgctrl = read_config(&sel,
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ptr + 2, 2);
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sc->psc_msi.emulated = 0;
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caplen = msi_caplen(sc->psc_msi.msgctrl);
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capptr = ptr;
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while (caplen > 0) {
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u32 = read_config(&sel, capptr, 4);
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pci_set_cfgdata32(pi, capptr, u32);
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caplen -= 4;
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capptr += 4;
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}
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} else if (cap == PCIY_MSIX) {
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/*
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* Copy the MSI-X capability
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*/
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sc->psc_msix.capoff = ptr;
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caplen = 12;
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msixcap_ptr = (uint32_t*) &msixcap;
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capptr = ptr;
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while (caplen > 0) {
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u32 = read_config(&sel, capptr, 4);
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*msixcap_ptr = u32;
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pci_set_cfgdata32(pi, capptr, u32);
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caplen -= 4;
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capptr += 4;
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msixcap_ptr++;
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}
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}
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ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
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}
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}
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if (sc->psc_msix.capoff != 0) {
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pi->pi_msix.pba_bar =
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msixcap.pba_info & PCIM_MSIX_BIR_MASK;
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pi->pi_msix.pba_offset =
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msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
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pi->pi_msix.table_bar =
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msixcap.table_info & PCIM_MSIX_BIR_MASK;
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pi->pi_msix.table_offset =
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msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
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pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
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pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
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/* Allocate the emulated MSI-X table array */
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table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
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pi->pi_msix.table = calloc(1, table_size);
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/* Mask all table entries */
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for (i = 0; i < pi->pi_msix.table_count; i++) {
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pi->pi_msix.table[i].vector_control |=
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PCIM_MSIX_VCTRL_MASK;
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}
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}
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#ifdef LEGACY_SUPPORT
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/*
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* If the passthrough device does not support MSI then craft a
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* MSI capability for it. We link the new MSI capability at the
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* head of the list of capabilities.
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*/
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if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
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int origptr, msiptr;
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origptr = read_config(&sel, PCIR_CAP_PTR, 1);
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msiptr = passthru_add_msicap(pi, 1, origptr);
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sc->psc_msi.capoff = msiptr;
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sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
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sc->psc_msi.emulated = 1;
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pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
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}
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#endif
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/* Make sure one of the capabilities is present */
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if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
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return (-1);
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else
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return (0);
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}
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static uint64_t
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msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
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{
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struct pci_devinst *pi;
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struct msix_table_entry *entry;
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uint8_t *src8;
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uint16_t *src16;
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uint32_t *src32;
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uint64_t *src64;
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uint64_t data;
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size_t entry_offset;
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int index;
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pi = sc->psc_pi;
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if (offset >= pi->pi_msix.pba_offset &&
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offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
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switch(size) {
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case 1:
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src8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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data = *src8;
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break;
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case 2:
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src16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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data = *src16;
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break;
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case 4:
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src32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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data = *src32;
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break;
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case 8:
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src64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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data = *src64;
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break;
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default:
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return (-1);
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}
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return (data);
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}
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if (offset < pi->pi_msix.table_offset)
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return (-1);
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offset -= pi->pi_msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= pi->pi_msix.table_count)
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return (-1);
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entry = &pi->pi_msix.table[index];
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entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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switch(size) {
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case 1:
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src8 = (uint8_t *)((void *)entry + entry_offset);
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data = *src8;
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break;
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case 2:
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src16 = (uint16_t *)((void *)entry + entry_offset);
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data = *src16;
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break;
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case 4:
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src32 = (uint32_t *)((void *)entry + entry_offset);
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data = *src32;
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break;
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case 8:
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src64 = (uint64_t *)((void *)entry + entry_offset);
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data = *src64;
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break;
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default:
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return (-1);
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}
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return (data);
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}
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static void
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msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
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uint64_t offset, int size, uint64_t data)
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{
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struct pci_devinst *pi;
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struct msix_table_entry *entry;
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uint8_t *dest8;
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uint16_t *dest16;
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uint32_t *dest32;
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uint64_t *dest64;
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size_t entry_offset;
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uint32_t vector_control;
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int index;
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pi = sc->psc_pi;
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if (offset >= pi->pi_msix.pba_offset &&
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offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
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switch(size) {
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case 1:
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dest8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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*dest8 = data;
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break;
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case 2:
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dest16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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*dest16 = data;
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break;
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case 4:
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dest32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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*dest32 = data;
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break;
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case 8:
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dest64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
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pi->pi_msix.pba_page_offset);
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*dest64 = data;
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break;
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default:
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break;
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}
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return;
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}
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if (offset < pi->pi_msix.table_offset)
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return;
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offset -= pi->pi_msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= pi->pi_msix.table_count)
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return;
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entry = &pi->pi_msix.table[index];
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entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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/* Only 4 byte naturally-aligned writes are supported */
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assert(size == 4);
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assert(entry_offset % 4 == 0);
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vector_control = entry->vector_control;
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dest32 = (uint32_t *)((void *)entry + entry_offset);
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*dest32 = data;
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/* If MSI-X hasn't been enabled, do nothing */
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if (pi->pi_msix.enabled) {
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/* If the entry is masked, don't set it up */
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if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
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(vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
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(void)vm_setup_pptdev_msix(ctx, vcpu,
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sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
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sc->psc_sel.pc_func, index, entry->addr,
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entry->msg_data, entry->vector_control);
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}
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}
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}
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static int
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init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
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{
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int b, s, f;
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int error, idx;
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size_t len, remaining;
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uint32_t table_size, table_offset;
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uint32_t pba_size, pba_offset;
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vm_paddr_t start;
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struct pci_devinst *pi = sc->psc_pi;
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assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
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b = sc->psc_sel.pc_bus;
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s = sc->psc_sel.pc_dev;
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f = sc->psc_sel.pc_func;
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/*
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* If the MSI-X table BAR maps memory intended for
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* other uses, it is at least assured that the table
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* either resides in its own page within the region,
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* or it resides in a page shared with only the PBA.
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*/
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table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
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table_size = pi->pi_msix.table_offset - table_offset;
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table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
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table_size = roundup2(table_size, 4096);
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idx = pi->pi_msix.table_bar;
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start = pi->pi_bar[idx].addr;
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remaining = pi->pi_bar[idx].size;
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if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) {
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pba_offset = pi->pi_msix.pba_offset;
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pba_size = pi->pi_msix.pba_size;
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if (pba_offset >= table_offset + table_size ||
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table_offset >= pba_offset + pba_size) {
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/*
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* If the PBA does not share a page with the MSI-x
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* tables, no PBA emulation is required.
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*/
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pi->pi_msix.pba_page = NULL;
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pi->pi_msix.pba_page_offset = 0;
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} else {
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/*
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* The PBA overlaps with either the first or last
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* page of the MSI-X table region. Map the
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* appropriate page.
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*/
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if (pba_offset <= table_offset)
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pi->pi_msix.pba_page_offset = table_offset;
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else
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pi->pi_msix.pba_page_offset = table_offset +
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table_size - 4096;
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pi->pi_msix.pba_page = mmap(NULL, 4096, PROT_READ |
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PROT_WRITE, MAP_SHARED, memfd, start +
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pi->pi_msix.pba_page_offset);
|
|
if (pi->pi_msix.pba_page == MAP_FAILED) {
|
|
warn(
|
|
"Failed to map PBA page for MSI-X on %d/%d/%d",
|
|
b, s, f);
|
|
return (-1);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Map everything before the MSI-X table */
|
|
if (table_offset > 0) {
|
|
len = table_offset;
|
|
error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
|
|
if (error)
|
|
return (error);
|
|
|
|
base += len;
|
|
start += len;
|
|
remaining -= len;
|
|
}
|
|
|
|
/* Skip the MSI-X table */
|
|
base += table_size;
|
|
start += table_size;
|
|
remaining -= table_size;
|
|
|
|
/* Map everything beyond the end of the MSI-X table */
|
|
if (remaining > 0) {
|
|
len = remaining;
|
|
error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
|
|
{
|
|
int i, error;
|
|
struct pci_devinst *pi;
|
|
struct pci_bar_io bar;
|
|
enum pcibar_type bartype;
|
|
uint64_t base, size;
|
|
|
|
pi = sc->psc_pi;
|
|
|
|
/*
|
|
* Initialize BAR registers
|
|
*/
|
|
for (i = 0; i <= PCI_BARMAX; i++) {
|
|
bzero(&bar, sizeof(bar));
|
|
bar.pbi_sel = sc->psc_sel;
|
|
bar.pbi_reg = PCIR_BAR(i);
|
|
|
|
if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
|
|
continue;
|
|
|
|
if (PCI_BAR_IO(bar.pbi_base)) {
|
|
bartype = PCIBAR_IO;
|
|
base = bar.pbi_base & PCIM_BAR_IO_BASE;
|
|
} else {
|
|
switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
|
|
case PCIM_BAR_MEM_64:
|
|
bartype = PCIBAR_MEM64;
|
|
break;
|
|
default:
|
|
bartype = PCIBAR_MEM32;
|
|
break;
|
|
}
|
|
base = bar.pbi_base & PCIM_BAR_MEM_BASE;
|
|
}
|
|
size = bar.pbi_length;
|
|
|
|
if (bartype != PCIBAR_IO) {
|
|
if (((base | size) & PAGE_MASK) != 0) {
|
|
warnx("passthru device %d/%d/%d BAR %d: "
|
|
"base %#lx or size %#lx not page aligned\n",
|
|
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
|
|
sc->psc_sel.pc_func, i, base, size);
|
|
return (-1);
|
|
}
|
|
}
|
|
|
|
/* Cache information about the "real" BAR */
|
|
sc->psc_bar[i].type = bartype;
|
|
sc->psc_bar[i].size = size;
|
|
sc->psc_bar[i].addr = base;
|
|
|
|
/* Allocate the BAR in the guest I/O or MMIO space */
|
|
error = pci_emul_alloc_pbar(pi, i, base, bartype, size);
|
|
if (error)
|
|
return (-1);
|
|
|
|
/* The MSI-X table needs special handling */
|
|
if (i == pci_msix_table_bar(pi)) {
|
|
error = init_msix_table(ctx, sc, base);
|
|
if (error)
|
|
return (-1);
|
|
} else if (bartype != PCIBAR_IO) {
|
|
/* Map the physical BAR in the guest MMIO space */
|
|
error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
|
sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
|
|
pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
|
|
if (error)
|
|
return (-1);
|
|
}
|
|
|
|
/*
|
|
* 64-bit BAR takes up two slots so skip the next one.
|
|
*/
|
|
if (bartype == PCIBAR_MEM64) {
|
|
i++;
|
|
assert(i <= PCI_BARMAX);
|
|
sc->psc_bar[i].type = PCIBAR_MEMHI64;
|
|
}
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
|
|
{
|
|
int error;
|
|
struct passthru_softc *sc;
|
|
|
|
error = 1;
|
|
sc = pi->pi_arg;
|
|
|
|
bzero(&sc->psc_sel, sizeof(struct pcisel));
|
|
sc->psc_sel.pc_bus = bus;
|
|
sc->psc_sel.pc_dev = slot;
|
|
sc->psc_sel.pc_func = func;
|
|
|
|
if (cfginitmsi(sc) != 0) {
|
|
warnx("failed to initialize MSI for PCI %d/%d/%d",
|
|
bus, slot, func);
|
|
goto done;
|
|
}
|
|
|
|
if (cfginitbar(ctx, sc) != 0) {
|
|
warnx("failed to initialize BARs for PCI %d/%d/%d",
|
|
bus, slot, func);
|
|
goto done;
|
|
}
|
|
|
|
error = 0; /* success */
|
|
done:
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
|
{
|
|
int bus, slot, func, error, memflags;
|
|
struct passthru_softc *sc;
|
|
#ifndef WITHOUT_CAPSICUM
|
|
cap_rights_t rights;
|
|
cap_ioctl_t pci_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR };
|
|
cap_ioctl_t io_ioctls[] = { IODEV_PIO };
|
|
#endif
|
|
|
|
sc = NULL;
|
|
error = 1;
|
|
|
|
#ifndef WITHOUT_CAPSICUM
|
|
cap_rights_init(&rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
|
|
#endif
|
|
|
|
memflags = vm_get_memflags(ctx);
|
|
if (!(memflags & VM_MEM_F_WIRED)) {
|
|
warnx("passthru requires guest memory to be wired");
|
|
goto done;
|
|
}
|
|
|
|
if (pcifd < 0) {
|
|
pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
|
|
if (pcifd < 0) {
|
|
warn("failed to open %s", _PATH_DEVPCI);
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
#ifndef WITHOUT_CAPSICUM
|
|
if (cap_rights_limit(pcifd, &rights) == -1 && errno != ENOSYS)
|
|
errx(EX_OSERR, "Unable to apply rights for sandbox");
|
|
if (cap_ioctls_limit(pcifd, pci_ioctls, nitems(pci_ioctls)) == -1 && errno != ENOSYS)
|
|
errx(EX_OSERR, "Unable to apply rights for sandbox");
|
|
#endif
|
|
|
|
if (iofd < 0) {
|
|
iofd = open(_PATH_DEVIO, O_RDWR, 0);
|
|
if (iofd < 0) {
|
|
warn("failed to open %s", _PATH_DEVIO);
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
#ifndef WITHOUT_CAPSICUM
|
|
if (cap_rights_limit(iofd, &rights) == -1 && errno != ENOSYS)
|
|
errx(EX_OSERR, "Unable to apply rights for sandbox");
|
|
if (cap_ioctls_limit(iofd, io_ioctls, nitems(io_ioctls)) == -1 && errno != ENOSYS)
|
|
errx(EX_OSERR, "Unable to apply rights for sandbox");
|
|
#endif
|
|
|
|
if (memfd < 0) {
|
|
memfd = open(_PATH_MEM, O_RDWR, 0);
|
|
if (memfd < 0) {
|
|
warn("failed to open %s", _PATH_MEM);
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
#ifndef WITHOUT_CAPSICUM
|
|
cap_rights_clear(&rights, CAP_IOCTL);
|
|
cap_rights_set(&rights, CAP_MMAP_RW);
|
|
if (cap_rights_limit(memfd, &rights) == -1 && errno != ENOSYS)
|
|
errx(EX_OSERR, "Unable to apply rights for sandbox");
|
|
#endif
|
|
|
|
if (opts == NULL ||
|
|
sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) {
|
|
warnx("invalid passthru options");
|
|
goto done;
|
|
}
|
|
|
|
if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
|
|
warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
|
|
bus, slot, func);
|
|
goto done;
|
|
}
|
|
|
|
sc = calloc(1, sizeof(struct passthru_softc));
|
|
|
|
pi->pi_arg = sc;
|
|
sc->psc_pi = pi;
|
|
|
|
/* initialize config space */
|
|
if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
|
|
goto done;
|
|
|
|
error = 0; /* success */
|
|
done:
|
|
if (error) {
|
|
free(sc);
|
|
vm_unassign_pptdev(ctx, bus, slot, func);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
bar_access(int coff)
|
|
{
|
|
if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
|
|
return (1);
|
|
else
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
msicap_access(struct passthru_softc *sc, int coff)
|
|
{
|
|
int caplen;
|
|
|
|
if (sc->psc_msi.capoff == 0)
|
|
return (0);
|
|
|
|
caplen = msi_caplen(sc->psc_msi.msgctrl);
|
|
|
|
if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
|
|
return (1);
|
|
else
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
msixcap_access(struct passthru_softc *sc, int coff)
|
|
{
|
|
if (sc->psc_msix.capoff == 0)
|
|
return (0);
|
|
|
|
return (coff >= sc->psc_msix.capoff &&
|
|
coff < sc->psc_msix.capoff + MSIX_CAPLEN);
|
|
}
|
|
|
|
static int
|
|
passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
|
int coff, int bytes, uint32_t *rv)
|
|
{
|
|
struct passthru_softc *sc;
|
|
|
|
sc = pi->pi_arg;
|
|
|
|
/*
|
|
* PCI BARs and MSI capability is emulated.
|
|
*/
|
|
if (bar_access(coff) || msicap_access(sc, coff))
|
|
return (-1);
|
|
|
|
#ifdef LEGACY_SUPPORT
|
|
/*
|
|
* Emulate PCIR_CAP_PTR if this device does not support MSI capability
|
|
* natively.
|
|
*/
|
|
if (sc->psc_msi.emulated) {
|
|
if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
|
|
return (-1);
|
|
}
|
|
#endif
|
|
|
|
/* Everything else just read from the device's config space */
|
|
*rv = read_config(&sc->psc_sel, coff, bytes);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
|
int coff, int bytes, uint32_t val)
|
|
{
|
|
int error, msix_table_entries, i;
|
|
struct passthru_softc *sc;
|
|
|
|
sc = pi->pi_arg;
|
|
|
|
/*
|
|
* PCI BARs are emulated
|
|
*/
|
|
if (bar_access(coff))
|
|
return (-1);
|
|
|
|
/*
|
|
* MSI capability is emulated
|
|
*/
|
|
if (msicap_access(sc, coff)) {
|
|
msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val);
|
|
|
|
error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
|
|
sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
|
|
pi->pi_msi.addr, pi->pi_msi.msg_data,
|
|
pi->pi_msi.maxmsgnum);
|
|
if (error != 0)
|
|
err(1, "vm_setup_pptdev_msi");
|
|
return (0);
|
|
}
|
|
|
|
if (msixcap_access(sc, coff)) {
|
|
msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val);
|
|
if (pi->pi_msix.enabled) {
|
|
msix_table_entries = pi->pi_msix.table_count;
|
|
for (i = 0; i < msix_table_entries; i++) {
|
|
error = vm_setup_pptdev_msix(ctx, vcpu,
|
|
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
|
|
sc->psc_sel.pc_func, i,
|
|
pi->pi_msix.table[i].addr,
|
|
pi->pi_msix.table[i].msg_data,
|
|
pi->pi_msix.table[i].vector_control);
|
|
|
|
if (error)
|
|
err(1, "vm_setup_pptdev_msix");
|
|
}
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
#ifdef LEGACY_SUPPORT
|
|
/*
|
|
* If this device does not support MSI natively then we cannot let
|
|
* the guest disable legacy interrupts from the device. It is the
|
|
* legacy interrupt that is triggering the virtual MSI to the guest.
|
|
*/
|
|
if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
|
|
if (coff == PCIR_COMMAND && bytes == 2)
|
|
val &= ~PCIM_CMD_INTxDIS;
|
|
}
|
|
#endif
|
|
|
|
write_config(&sc->psc_sel, coff, bytes, val);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
|
|
uint64_t offset, int size, uint64_t value)
|
|
{
|
|
struct passthru_softc *sc;
|
|
struct iodev_pio_req pio;
|
|
|
|
sc = pi->pi_arg;
|
|
|
|
if (baridx == pci_msix_table_bar(pi)) {
|
|
msix_table_write(ctx, vcpu, sc, offset, size, value);
|
|
} else {
|
|
assert(pi->pi_bar[baridx].type == PCIBAR_IO);
|
|
bzero(&pio, sizeof(struct iodev_pio_req));
|
|
pio.access = IODEV_PIO_WRITE;
|
|
pio.port = sc->psc_bar[baridx].addr + offset;
|
|
pio.width = size;
|
|
pio.val = value;
|
|
|
|
(void)ioctl(iofd, IODEV_PIO, &pio);
|
|
}
|
|
}
|
|
|
|
static uint64_t
|
|
passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
|
|
uint64_t offset, int size)
|
|
{
|
|
struct passthru_softc *sc;
|
|
struct iodev_pio_req pio;
|
|
uint64_t val;
|
|
|
|
sc = pi->pi_arg;
|
|
|
|
if (baridx == pci_msix_table_bar(pi)) {
|
|
val = msix_table_read(sc, offset, size);
|
|
} else {
|
|
assert(pi->pi_bar[baridx].type == PCIBAR_IO);
|
|
bzero(&pio, sizeof(struct iodev_pio_req));
|
|
pio.access = IODEV_PIO_READ;
|
|
pio.port = sc->psc_bar[baridx].addr + offset;
|
|
pio.width = size;
|
|
pio.val = 0;
|
|
|
|
(void)ioctl(iofd, IODEV_PIO, &pio);
|
|
|
|
val = pio.val;
|
|
}
|
|
|
|
return (val);
|
|
}
|
|
|
|
struct pci_devemu passthru = {
|
|
.pe_emu = "passthru",
|
|
.pe_init = passthru_init,
|
|
.pe_cfgwrite = passthru_cfgwrite,
|
|
.pe_cfgread = passthru_cfgread,
|
|
.pe_barwrite = passthru_write,
|
|
.pe_barread = passthru_read,
|
|
};
|
|
PCI_EMUL_SET(passthru);
|