e41e815e5c
This interface also appears in the AT91SAM9260 and '61 as well as the AVR32 based micros from Atmel. We don't yet support write protect or hot-swap in this bridge driver.
129 lines
7.8 KiB
C
129 lines
7.8 KiB
C
/*-
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* Copyright (c) 2006 Berndt Walter. All rights reserved.
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91QDMMCREG_H
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#define ARM_AT91_AT91QDMMCREG_H
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#define MMC_MAX 30
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#define MCI_CR 0x00 /* MCI Control Register */
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#define MCI_MR 0x04 /* MCI Mode Register */
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#define MCI_DTOR 0x08 /* MCI Data Timeout Register */
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#define MCI_SDCR 0x0c /* MCI SD Card Register */
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#define MCI_ARGR 0x10 /* MCI Argument Register */
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#define MCI_CMDR 0x14 /* MCI Command Register */
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#define MCI_RSPR 0x20 /* MCI Response Registers - 4 of them */
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#define MCI_RDR 0x30 /* MCI Receive Data Register */
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#define MCI_TDR 0x34 /* MCI Transmit Data Register */
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#define MCI_SR 0x40 /* MCI Status Register */
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#define MCI_IER 0x44 /* MCI Interrupt Enable Register */
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#define MCI_IDR 0x48 /* MCI Interrupt Disable Register */
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#define MCI_IMR 0x4c /* MCI Interrupt Mask Register */
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/* -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- */
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#define MCI_CR_MCIEN (0x1u << 0) /* (MCI) Multimedia Interface Enable */
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#define MCI_CR_MCIDIS (0x1u << 1) /* (MCI) Multimedia Interface Disable */
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#define MCI_CR_PWSEN (0x1u << 2) /* (MCI) Power Save Mode Enable */
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#define MCI_CR_PWSDIS (0x1u << 3) /* (MCI) Power Save Mode Disable */
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#define MCI_CR_SWRST (0x1u << 7) /* (MCI) Software Reset */
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/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */
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#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */
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#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */
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#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */
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#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */
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#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */
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/* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- */
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#define MCI_DTOR_DTOCYC (0xfu << 0) /* (MCI) Data Timeout Cycle Number */
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#define MCI_DTOR_DTOMUL (0x7u << 4) /* (MCI) Data Timeout Multiplier */
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#define MCI_DTOR_DTOMUL_1 (0x0u << 4) /* (MCI) DTOCYC x 1 */
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#define MCI_DTOR_DTOMUL_16 (0x1u << 4) /* (MCI) DTOCYC x 16 */
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#define MCI_DTOR_DTOMUL_128 (0x2u << 4) /* (MCI) DTOCYC x 128 */
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#define MCI_DTOR_DTOMUL_256 (0x3u << 4) /* (MCI) DTOCYC x 256 */
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#define MCI_DTOR_DTOMUL_1k (0x4u << 4) /* (MCI) DTOCYC x 1024 */
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#define MCI_DTOR_DTOMUL_4k (0x5u << 4) /* (MCI) DTOCYC x 4096 */
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#define MCI_DTOR_DTOMUL_64k (0x6u << 4) /* (MCI) DTOCYC x 65536 */
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#define MCI_DTOR_DTOMUL_1M (0x7u << 4) /* (MCI) DTOCYC x 1048576 */
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/* -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- */
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#define MCI_SDCR_SDCSEL (0x1u << 0) /* (MCI) SD Card Selector */
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#define MCI_SDCR_SDCBUS (0x1u << 7) /* (MCI) SD Card Bus Width */
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/* -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- */
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#define MCI_CMDR_CMDNB (0x1Fu << 0) /* (MCI) Command Number */
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#define MCI_CMDR_RSPTYP (0x3u << 6) /* (MCI) Response Type */
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#define MCI_CMDR_RSPTYP_NO (0x0u << 6) /* (MCI) No response */
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#define MCI_CMDR_RSPTYP_48 (0x1u << 6) /* (MCI) 48-bit response */
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#define MCI_CMDR_RSPTYP_136 (0x2u << 6) /* (MCI) 136-bit response */
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#define MCI_CMDR_SPCMD (0x7u << 8) /* (MCI) Special CMD */
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#define MCI_CMDR_SPCMD_NONE (0x0u << 8) /* (MCI) Not a special CMD */
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#define MCI_CMDR_SPCMD_INIT (0x1u << 8) /* (MCI) Initialization CMD */
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#define MCI_CMDR_SPCMD_SYNC (0x2u << 8) /* (MCI) Synchronized CMD */
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#define MCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /* (MCI) Interrupt command */
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#define MCI_CMDR_SPCMD_IT_REP (0x5u << 8) /* (MCI) Interrupt response */
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#define MCI_CMDR_OPDCMD (0x1u << 11) /* (MCI) Open Drain Command */
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#define MCI_CMDR_MAXLAT (0x1u << 12) /* (MCI) Maximum Latency for Command to respond */
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#define MCI_CMDR_TRCMD (0x3u << 16) /* (MCI) Transfer CMD */
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#define MCI_CMDR_TRCMD_NO (0x0u << 16) /* (MCI) No transfer */
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#define MCI_CMDR_TRCMD_START (0x1u << 16) /* (MCI) Start transfer */
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#define MCI_CMDR_TRCMD_STOP (0x2u << 16) /* (MCI) Stop transfer */
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#define MCI_CMDR_TRDIR (0x1u << 18) /* (MCI) Transfer Direction */
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#define MCI_CMDR_TRTYP (0x3u << 19) /* (MCI) Transfer Type */
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#define MCI_CMDR_TRTYP_BLOCK (0x0u << 19) /* (MCI) Block Transfer type */
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#define MCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /* (MCI) Multiple Block transfer type */
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#define MCI_CMDR_TRTYP_STREAM (0x2u << 19) /* (MCI) Stream transfer type */
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/* -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- */
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#define MCI_SR_CMDRDY (0x1u << 0) /* (MCI) Command Ready flag */
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#define MCI_SR_RXRDY (0x1u << 1) /* (MCI) RX Ready flag */
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#define MCI_SR_TXRDY (0x1u << 2) /* (MCI) TX Ready flag */
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#define MCI_SR_BLKE (0x1u << 3) /* (MCI) Data Block Transfer Ended flag */
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#define MCI_SR_DTIP (0x1u << 4) /* (MCI) Data Transfer in Progress flag */
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#define MCI_SR_NOTBUSY (0x1u << 5) /* (MCI) Data Line Not Busy flag */
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#define MCI_SR_ENDRX (0x1u << 6) /* (MCI) End of RX Buffer flag */
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#define MCI_SR_ENDTX (0x1u << 7) /* (MCI) End of TX Buffer flag */
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#define MCI_SR_RXBUFF (0x1u << 14) /* (MCI) RX Buffer Full flag */
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#define MCI_SR_TXBUFE (0x1u << 15) /* (MCI) TX Buffer Empty flag */
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#define MCI_SR_RINDE (0x1u << 16) /* (MCI) Response Index Error flag */
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#define MCI_SR_RDIRE (0x1u << 17) /* (MCI) Response Direction Error flag */
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#define MCI_SR_RCRCE (0x1u << 18) /* (MCI) Response CRC Error flag */
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#define MCI_SR_RENDE (0x1u << 19) /* (MCI) Response End Bit Error flag */
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#define MCI_SR_RTOE (0x1u << 20) /* (MCI) Response Time-out Error flag */
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#define MCI_SR_DCRCE (0x1u << 21) /* (MCI) data CRC Error flag */
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#define MCI_SR_DTOE (0x1u << 22) /* (MCI) Data timeout Error flag */
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#define MCI_SR_OVRE (0x1u << 30) /* (MCI) Overrun flag */
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#define MCI_SR_UNRE (0x1u << 31) /* (MCI) Underrun flag */
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/* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- */
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/* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- */
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/* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- */
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#define MCI_SR_ERROR (MCI_SR_UNRE | MCI_SR_OVRE | MCI_SR_DTOE | \
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MCI_SR_DCRCE | MCI_SR_RTOE | MCI_SR_RENDE | \
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MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE)
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#define AT91C_BUS_WIDTH_1BIT 0x00
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#define AT91C_BUS_WIDTH_4BITS 0x02
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#endif /* ARM_AT91_AT91QDMMCREG_H */
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