108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/*-
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_
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#define _POWERPC_POWERMAC_UNINORTHVAR_H_
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <powerpc/ofw/ofw_pci.h>
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struct uninorth_softc {
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struct ofw_pci_softc pci_sc;
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vm_offset_t sc_addr;
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vm_offset_t sc_data;
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int sc_ver;
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};
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struct unin_chip_softc {
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uint64_t sc_physaddr;
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uint64_t sc_size;
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vm_offset_t sc_addr;
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struct rman sc_mem_rman;
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int sc_version;
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};
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/*
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* Format of a unin reg property entry.
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*/
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struct unin_chip_reg {
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u_int32_t mr_base;
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u_int32_t mr_size;
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};
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/*
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* Per unin device structure.
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*/
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struct unin_chip_devinfo {
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int udi_interrupts[6];
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int udi_ninterrupts;
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int udi_base;
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struct ofw_bus_devinfo udi_obdinfo;
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struct resource_list udi_resources;
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};
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/*
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* Version register
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*/
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#define UNIN_VERS 0x0
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/*
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* Clock-control register
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*/
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#define UNIN_CLOCKCNTL 0x20
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#define UNIN_CLOCKCNTL_GMAC 0x2
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/*
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* Power management register
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*/
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#define UNIN_PWR_MGMT 0x30
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#define UNIN_PWR_NORMAL 0x00
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#define UNIN_PWR_IDLE2 0x01
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#define UNIN_PWR_SLEEP 0x02
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#define UNIN_PWR_SAVE 0x03
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#define UNIN_PWR_MASK 0x03
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/*
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* Hardware initialization state register
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*/
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#define UNIN_HWINIT_STATE 0x70
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#define UNIN_SLEEPING 0x01
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#define UNIN_RUNNING 0x02
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/*
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* Toggle registers
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*/
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#define UNIN_TOGGLE_REG 0xe0
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#define UNIN_MPIC_RESET 0x2
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#define UNIN_MPIC_OUTPUT_ENABLE 0x4
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extern int unin_chip_sleep(device_t dev, int idle);
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extern int unin_chip_wake(device_t dev);
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#endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */
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