17696c12f5
Tested on Spike simulator with 2 and 16 cores (tlb enabled), so set MAXCPU to 16 at this time. This uses FDT data to get information about CPUs (code based on arm64 mp_machdep). Invalidate entire TLB cache as it is the only way yet. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
48 lines
1.5 KiB
Plaintext
48 lines
1.5 KiB
Plaintext
# $FreeBSD$
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crypto/blowfish/bf_enc.c optional crypto | ipsec
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crypto/des/des_enc.c optional crypto | ipsec | netsmb
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dev/ofw/ofw_cpu.c optional fdt
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kern/kern_clocksource.c standard
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kern/subr_dummy_vdso_tc.c standard
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libkern/bcmp.c standard
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libkern/ffs.c standard
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libkern/ffsl.c standard
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libkern/fls.c standard
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libkern/flsl.c standard
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libkern/flsll.c standard
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libkern/memmove.c standard
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libkern/memset.c standard
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riscv/htif/htif.c standard
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riscv/htif/htif_block.c standard
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riscv/htif/htif_console.c standard
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riscv/riscv/autoconf.c standard
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riscv/riscv/bcopy.c standard
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riscv/riscv/bus_machdep.c standard
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riscv/riscv/busdma_machdep.c standard
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riscv/riscv/clock.c standard
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riscv/riscv/copyinout.S standard
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riscv/riscv/copystr.c standard
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riscv/riscv/cpufunc_asm.S standard
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riscv/riscv/devmap.c standard
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riscv/riscv/dump_machdep.c standard
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riscv/riscv/elf_machdep.c standard
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riscv/riscv/intr_machdep.c standard
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riscv/riscv/in_cksum.c optional inet | inet6
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riscv/riscv/identcpu.c standard
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riscv/riscv/locore.S standard no-obj
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riscv/riscv/machdep.c standard
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riscv/riscv/minidump_machdep.c standard
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riscv/riscv/mp_machdep.c optional smp
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riscv/riscv/mem.c standard
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riscv/riscv/nexus.c standard
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riscv/riscv/pmap.c standard
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riscv/riscv/stack_machdep.c optional ddb | stack
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riscv/riscv/support.S standard
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riscv/riscv/swtch.S standard
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riscv/riscv/sys_machdep.c standard
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riscv/riscv/trap.c standard
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riscv/riscv/timer.c standard
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riscv/riscv/uio_machdep.c standard
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riscv/riscv/uma_machdep.c standard
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riscv/riscv/vm_machdep.c standard
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