Jayachandran C. 2e4e56742e Clean up and update sys/mips/rmi/rmi_mips_exts.h ... - Provide 64 bit implementations for some macros. On n64 and n32, don't split 64 bit values. - No need for 32 bit ops for control registers. - Fix few bugs (write control reg, write_c0_register64). - Re-write EIRR/EIMR/CPUID operations using read_c0_registerXX, no need of inline assembly. - rename control reg access functions to avoid phnx, update callers. - stlye/whitespace fixes.		2010-09-09 17:45:48 +00:00
..
adm5120	Remove some stray ';'s	2010-05-13 01:50:29 +00:00
alchemy	Hack to make ALCHEMY compile again...	2010-02-18 19:41:38 +00:00
atheros	Migrate if_arge to use the PLL cpuops.	2010-08-19 16:29:08 +00:00
cavium	o) Add the "octusb" controller which supports the first port of the Octeon	2010-07-20 19:32:25 +00:00
compile
conf	Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.	2010-08-13 12:56:00 +00:00
idt
include	Remove misleading comment in pte.h. MIPS PTE entries are software managed	2010-08-30 08:23:22 +00:00
malta	Fix MALTA64 build.	2010-04-19 09:03:34 +00:00
mips	Whitespace fixes - indent with tabs instead of spaces.	2010-09-07 06:02:43 +00:00
rmi	Clean up and update sys/mips/rmi/rmi_mips_exts.h	2010-09-09 17:45:48 +00:00
sentry5
sibyte	Remove redundant declaration of 'pcib_driver' class from sb_zbpci.c. This	2010-08-06 07:03:22 +00:00