9ca4041b6c
-It has new hardware support -It uses a new method of TX cleanup called Head Write Back -It includes the provisional generic TCP LRO feature contributed by Myricom and made general purpose by me. This should move into the stack upon approval but for this driver drop its in here. -Also bug fixes and etc... MFC in a week if no serious issues arise.
672 lines
19 KiB
C
672 lines
19 KiB
C
/******************************************************************************
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Copyright (c) 2001-2008, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "ixgbe_api.h"
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#include "ixgbe_common.h"
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#include "ixgbe_phy.h"
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/**
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* ixgbe_init_phy_ops_generic - Inits PHY function ptrs
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* @hw: pointer to the hardware structure
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*
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* Initialize the function pointers.
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**/
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s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
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{
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struct ixgbe_phy_info *phy = &hw->phy;
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/* PHY */
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phy->ops.identify = &ixgbe_identify_phy_generic;
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phy->ops.reset = &ixgbe_reset_phy_generic;
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phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
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phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
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phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
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phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
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phy->ops.check_link = NULL;
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phy->ops.get_firmware_version = NULL;
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_identify_phy_generic - Get physical layer module
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* @hw: pointer to hardware structure
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*
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* Determines the physical layer module found on the current adapter.
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**/
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s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
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{
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s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
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u32 phy_addr;
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if (hw->phy.type == ixgbe_phy_unknown) {
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for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
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if (ixgbe_validate_phy_addr(hw, phy_addr)) {
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hw->phy.addr = phy_addr;
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ixgbe_get_phy_id(hw);
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hw->phy.type =
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ixgbe_get_phy_type_from_id(hw->phy.id);
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status = IXGBE_SUCCESS;
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break;
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}
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}
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} else {
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status = IXGBE_SUCCESS;
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}
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return status;
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}
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/**
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* ixgbe_validate_phy_addr - Determines phy address is valid
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* @hw: pointer to hardware structure
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*
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**/
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bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
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{
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u16 phy_id = 0;
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bool valid = FALSE;
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hw->phy.addr = phy_addr;
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hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
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if (phy_id != 0xFFFF && phy_id != 0x0)
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valid = TRUE;
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return valid;
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}
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/**
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* ixgbe_get_phy_id - Get the phy type
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* @hw: pointer to hardware structure
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*
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**/
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s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
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{
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u32 status;
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u16 phy_id_high = 0;
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u16 phy_id_low = 0;
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&phy_id_high);
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if (status == IXGBE_SUCCESS) {
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hw->phy.id = (u32)(phy_id_high << 16);
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&phy_id_low);
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hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
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hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
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}
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return status;
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}
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/**
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* ixgbe_get_phy_type_from_id - Get the phy type
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* @hw: pointer to hardware structure
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*
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**/
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enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
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{
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enum ixgbe_phy_type phy_type;
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switch (phy_id) {
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case TN1010_PHY_ID:
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phy_type = ixgbe_phy_tn;
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break;
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case QT2022_PHY_ID:
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phy_type = ixgbe_phy_qt;
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break;
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case ATH_PHY_ID:
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phy_type = ixgbe_phy_nl;
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break;
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default:
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phy_type = ixgbe_phy_unknown;
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break;
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}
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DEBUGOUT1("phy type found is %d\n", phy_type);
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return phy_type;
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}
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/**
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* ixgbe_reset_phy_generic - Performs a PHY reset
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* @hw: pointer to hardware structure
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**/
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s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
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{
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/*
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* Perform soft PHY reset to the PHY_XS.
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* This will cause a soft reset to the PHY
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*/
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return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
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IXGBE_MDIO_PHY_XS_DEV_TYPE,
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IXGBE_MDIO_PHY_XS_RESET);
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}
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/**
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* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
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* @hw: pointer to hardware structure
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* @reg_addr: 32 bit address of PHY register to read
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* @phy_data: Pointer to read data from PHY register
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**/
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s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 *phy_data)
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{
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u32 command;
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u32 i;
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u32 data;
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s32 status = IXGBE_SUCCESS;
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u16 gssr;
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if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
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gssr = IXGBE_GSSR_PHY1_SM;
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else
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gssr = IXGBE_GSSR_PHY0_SM;
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if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
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status = IXGBE_ERR_SWFW_SYNC;
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if (status == IXGBE_SUCCESS) {
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/* Setup and write the address cycle command */
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle completed.
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* The MDI Command bit will clear when the operation is
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* complete
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*/
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for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
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usec_delay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
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break;
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}
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
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DEBUGOUT("PHY address command did not complete.\n");
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status = IXGBE_ERR_PHY;
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}
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if (status == IXGBE_SUCCESS) {
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/*
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* Address cycle complete, setup and write the read
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* command
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*/
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle
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* completed. The MDI Command bit will clear when the
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* operation is complete
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*/
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for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
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usec_delay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
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break;
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
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DEBUGOUT("PHY read command didn't complete\n");
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status = IXGBE_ERR_PHY;
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} else {
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/*
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* Read operation is complete. Get the data
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* from MSRWD
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*/
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data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
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data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
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*phy_data = (u16)(data);
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}
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}
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ixgbe_release_swfw_sync(hw, gssr);
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}
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return status;
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}
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/**
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* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
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* @hw: pointer to hardware structure
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* @reg_addr: 32 bit PHY register to write
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* @device_type: 5 bit device type
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* @phy_data: Data to write to the PHY register
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**/
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s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 phy_data)
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{
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u32 command;
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u32 i;
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s32 status = IXGBE_SUCCESS;
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u16 gssr;
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if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
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gssr = IXGBE_GSSR_PHY1_SM;
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else
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gssr = IXGBE_GSSR_PHY0_SM;
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if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
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status = IXGBE_ERR_SWFW_SYNC;
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if (status == IXGBE_SUCCESS) {
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/* Put the data in the MDI single read and write data register*/
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IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
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/* Setup and write the address cycle command */
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle completed.
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* The MDI Command bit will clear when the operation is
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* complete
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*/
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for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
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usec_delay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
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break;
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
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DEBUGOUT("PHY address cmd didn't complete\n");
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status = IXGBE_ERR_PHY;
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}
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if (status == IXGBE_SUCCESS) {
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/*
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* Address cycle complete, setup and write the write
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* command
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*/
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle
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* completed. The MDI Command bit will clear when the
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* operation is complete
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*/
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for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
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usec_delay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
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break;
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
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DEBUGOUT("PHY address cmd didn't complete\n");
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status = IXGBE_ERR_PHY;
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}
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}
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ixgbe_release_swfw_sync(hw, gssr);
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}
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return status;
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}
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/**
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* ixgbe_setup_phy_link_generic - Set and restart autoneg
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* @hw: pointer to hardware structure
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*
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* Restart autonegotiation and PHY and waits for completion.
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**/
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s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
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{
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s32 status = IXGBE_NOT_IMPLEMENTED;
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u32 time_out;
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u32 max_time_out = 10;
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u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
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/*
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* Set advertisement settings in PHY based on autoneg_advertised
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* settings. If autoneg_advertised = 0, then advertise default values
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* tnx devices cannot be "forced" to a autoneg 10G and fail. But can
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* for a 1G.
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*/
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hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
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if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
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autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
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else
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autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
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hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
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/* Restart PHY autonegotiation and wait for completion */
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hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
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autoneg_reg |= IXGBE_MII_RESTART;
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hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
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/* Wait for autonegotiation to finish */
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for (time_out = 0; time_out < max_time_out; time_out++) {
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usec_delay(10);
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/* Restart PHY autonegotiation and wait for completion */
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_reg);
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autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
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if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
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status = IXGBE_SUCCESS;
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break;
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}
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}
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if (time_out == max_time_out)
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status = IXGBE_ERR_LINK_SETUP;
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return status;
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}
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/**
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* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
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* @hw: pointer to hardware structure
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* @speed: new link speed
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* @autoneg: TRUE if autonegotiation enabled
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**/
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s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
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ixgbe_link_speed speed,
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bool autoneg,
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bool autoneg_wait_to_complete)
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{
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UNREFERENCED_PARAMETER(autoneg);
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UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
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/*
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* Clear autoneg_advertised and set new values based on input link
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* speed.
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*/
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hw->phy.autoneg_advertised = 0;
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if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
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}
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if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
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}
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/* Setup link based on the new speed settings */
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hw->phy.ops.setup_link(hw);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_check_phy_link_tnx - Determine link and speed status
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* @hw: pointer to hardware structure
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*
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* Reads the VS1 register to determine if link is up and the current speed for
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* the PHY.
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**/
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s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *link_up)
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{
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s32 status = IXGBE_SUCCESS;
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u32 time_out;
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u32 max_time_out = 10;
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u16 phy_link = 0;
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u16 phy_speed = 0;
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u16 phy_data = 0;
|
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|
|
/* Initialize speed and link to default case */
|
|
*link_up = FALSE;
|
|
*speed = IXGBE_LINK_SPEED_10GB_FULL;
|
|
|
|
/*
|
|
* Check current speed and link status of the PHY register.
|
|
* This is a vendor specific register and may have to
|
|
* be changed for other copper PHYs.
|
|
*/
|
|
for (time_out = 0; time_out < max_time_out; time_out++) {
|
|
usec_delay(10);
|
|
status = hw->phy.ops.read_reg(hw,
|
|
IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
|
|
IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
|
|
&phy_data);
|
|
phy_link = phy_data &
|
|
IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
|
|
phy_speed = phy_data &
|
|
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
|
|
if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
|
|
*link_up = TRUE;
|
|
if (phy_speed ==
|
|
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
|
|
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
|
|
* @hw: pointer to hardware structure
|
|
* @firmware_version: pointer to the PHY Firmware Version
|
|
**/
|
|
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
|
u16 *firmware_version)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
|
|
status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
|
|
IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
|
|
firmware_version);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_reset_phy_nl - Performs a PHY reset
|
|
* @hw: pointer to hardware structure
|
|
**/
|
|
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
|
|
{
|
|
u16 phy_offset, control, eword, edata, list_crc, block_crc, id, sfp_id;
|
|
bool end_data = FALSE;
|
|
u16 list_offset, data_offset;
|
|
u16 phy_data = 0;
|
|
s32 ret_val = IXGBE_SUCCESS;
|
|
u32 i;
|
|
|
|
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
|
|
IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
|
|
|
|
/* reset the PHY and poll for completion */
|
|
hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
|
|
IXGBE_MDIO_PHY_XS_DEV_TYPE,
|
|
(phy_data | IXGBE_MDIO_PHY_XS_RESET));
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
|
|
IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
|
|
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0 )
|
|
break;
|
|
msec_delay(10);
|
|
}
|
|
|
|
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
|
|
DEBUGOUT("PHY reset did not complete.\n");
|
|
ret_val = IXGBE_ERR_PHY;
|
|
goto out;
|
|
}
|
|
|
|
/* read offset to PHY init contents */
|
|
hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, &list_offset);
|
|
|
|
if ((!list_offset) || (list_offset == 0xFFFF)) {
|
|
ret_val = IXGBE_ERR_PHY;
|
|
goto out;
|
|
}
|
|
|
|
/* Acquire the CRC */
|
|
hw->eeprom.ops.read(hw, list_offset, &list_crc);
|
|
|
|
/* Shift offset to first ID word */
|
|
list_offset++;
|
|
|
|
/* determine the sfp sequence based on device ID */
|
|
switch (hw->device_id) {
|
|
case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
|
|
sfp_id = 0;
|
|
break;
|
|
case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
|
|
sfp_id = 1;
|
|
break;
|
|
default:
|
|
ret_val = IXGBE_ERR_PHY;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Find the matching sfp ID in the EEPROM
|
|
* and program the init sequence
|
|
*/
|
|
hw->eeprom.ops.read(hw, list_offset, &id);
|
|
|
|
while (!((id == IXGBE_CONTROL_EOL_NL) || (end_data == TRUE))) {
|
|
if (id == sfp_id) {
|
|
list_offset++;
|
|
hw->eeprom.ops.read(hw, list_offset, &data_offset);
|
|
if ((!data_offset) || (data_offset == 0xFFFF))
|
|
break;
|
|
ret_val = hw->eeprom.ops.read(hw, data_offset,
|
|
&block_crc);
|
|
data_offset++;
|
|
while (!end_data) {
|
|
/*
|
|
* Read control word from PHY init contents
|
|
* offset
|
|
*/
|
|
ret_val = hw->eeprom.ops.read(hw, data_offset,
|
|
&eword);
|
|
control = (eword & IXGBE_CONTROL_MASK_NL) >>
|
|
IXGBE_CONTROL_SHIFT_NL;
|
|
edata = eword & IXGBE_DATA_MASK_NL;
|
|
switch (control) {
|
|
case IXGBE_DELAY_NL:
|
|
data_offset++;
|
|
DEBUGOUT1("DELAY: %d MS\n", edata);
|
|
msec_delay(edata);
|
|
break;
|
|
case IXGBE_DATA_NL:
|
|
DEBUGOUT("DATA: \n");
|
|
data_offset++;
|
|
hw->eeprom.ops.read(hw, data_offset++,
|
|
&phy_offset);
|
|
for (i = 0; i < edata; i++) {
|
|
hw->eeprom.ops.read(hw,
|
|
data_offset,
|
|
&eword);
|
|
hw->phy.ops.write_reg(hw,
|
|
phy_offset,
|
|
IXGBE_TWINAX_DEV,
|
|
eword);
|
|
DEBUGOUT2("Wrote %4.4x to %4.4x\n",
|
|
eword, phy_offset);
|
|
data_offset++;
|
|
phy_offset++;
|
|
}
|
|
break;
|
|
case IXGBE_CONTROL_NL:
|
|
data_offset++;
|
|
DEBUGOUT("CONTROL: \n");
|
|
if (edata == IXGBE_CONTROL_EOL_NL) {
|
|
DEBUGOUT("EOL\n");
|
|
end_data = TRUE;
|
|
} else if (edata == IXGBE_CONTROL_SOL_NL) {
|
|
DEBUGOUT("SOL\n");
|
|
} else {
|
|
DEBUGOUT("Bad control value\n");
|
|
ret_val = IXGBE_ERR_PHY;
|
|
goto out;
|
|
}
|
|
break;
|
|
default:
|
|
DEBUGOUT("Bad control type\n");
|
|
ret_val = IXGBE_ERR_PHY;
|
|
goto out;
|
|
}
|
|
}
|
|
} else {
|
|
list_offset += 2;
|
|
ret_val = hw->eeprom.ops.read(hw, list_offset, &id);
|
|
if (ret_val)
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|