21221d1f6b
The last 12 bits of the limit registers have to be set to 1. These bits are not significant in bridge BARs and are 0 on read, but the bits are valid in the swap limit register and needs to be set.
895 lines
22 KiB
C
895 lines
22 KiB
C
/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/types.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/rman.h>
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#include <sys/pciio.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pci_private.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_cpu.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <machine/intr_machdep.h>
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#include <machine/cpuregs.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/interrupt.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/pic.h>
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#include <mips/nlm/hal/bridge.h>
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#include <mips/nlm/hal/gbu.h>
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#include <mips/nlm/hal/pcibus.h>
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#include <mips/nlm/hal/uart.h>
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#include <mips/nlm/xlp.h>
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#include "pcib_if.h"
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#include "pci_if.h"
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#define EMUL_MEM_START 0x16000000UL
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#define EMUL_MEM_END 0x18ffffffUL
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/* SoC device qurik handling */
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static int irt_irq_map[4 * 256];
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static int irq_irt_map[64];
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static void
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xlp_add_irq(int node, int irt, int irq)
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{
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int nodeirt = node * 256 + irt;
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irt_irq_map[nodeirt] = irq;
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irq_irt_map[irq] = nodeirt;
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}
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int
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xlp_irq_to_irt(int irq)
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{
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return irq_irt_map[irq];
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}
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int
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xlp_irt_to_irq(int nodeirt)
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{
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return irt_irq_map[nodeirt];
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}
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/* Override PCI a bit for SoC devices */
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enum {
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INTERNAL_DEV = 0x1, /* internal device, skip on enumeration */
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MEM_RES_EMUL = 0x2, /* no MEM or IO bar, custom res alloc */
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SHARED_IRQ = 0x4,
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DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */
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};
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struct soc_dev_desc {
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u_int devid; /* device ID */
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int irqbase; /* start IRQ */
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u_int flags; /* flags */
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int ndevs; /* to keep track of number of devices */
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};
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struct soc_dev_desc xlp_dev_desc[] = {
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{ PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV },
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{ PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV },
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{ PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV },
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{ PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32},
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{ PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 },
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{ PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL },
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{ PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL },
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{ PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 }
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};
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struct xlp_devinfo {
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struct pci_devinfo pcidev;
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int irq;
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int flags;
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u_long mem_res_start;
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};
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static __inline struct soc_dev_desc *
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xlp_find_soc_desc(int devid)
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{
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struct soc_dev_desc *p;
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int i, n;
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n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]);
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for (i = 0, p = xlp_dev_desc; i < n; i++, p++)
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if (p->devid == devid)
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return (p);
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return (NULL);
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}
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static struct resource *
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xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct resource *r;
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struct xlp_devinfo *xlp_devinfo;
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int busno;
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/*
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* Do custom allocation for MEMORY resource for SoC device if
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* MEM_RES_EMUL flag is set
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*/
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busno = pci_get_bus(child);
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if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) && busno == 0) {
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xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child);
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if ((xlp_devinfo->flags & MEM_RES_EMUL) != 0) {
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/* no emulation for IO ports */
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if (type == SYS_RES_IOPORT)
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return (NULL);
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start = xlp_devinfo->mem_res_start;
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count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ;
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/* MMC needs to 2 slots with rids 16 and 20 and a
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* fixup for size */
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if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) {
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count = 0x100;
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if (*rid == 16)
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; /* first slot already setup */
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else if (*rid == 20)
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start += 0x100; /* second slot */
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else
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return (NULL);
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}
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end = start + count - 1;
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r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
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type, rid, start, end, count, flags);
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if (r == NULL)
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return (NULL);
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if ((xlp_devinfo->flags & DEV_MMIO32) != 0)
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rman_set_bustag(r, rmi_uart_bus_space);
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return (r);
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}
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}
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/* Not custom alloc, use PCI code */
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return (pci_alloc_resource(bus, child, type, rid, start, end, count,
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flags));
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}
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static int
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xlp_pci_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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u_long start;
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/* If custom alloc, handle that */
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start = rman_get_start(r);
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if (type == SYS_RES_MEMORY && pci_get_bus(child) == 0 &&
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start >= EMUL_MEM_START && start <= EMUL_MEM_END)
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return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
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type, rid, r));
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/* use default PCI function */
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return (bus_generic_rl_release_resource(bus, child, type, rid, r));
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}
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static void
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xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f)
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{
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struct pci_devinfo *dinfo;
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struct xlp_devinfo *xlp_dinfo;
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struct soc_dev_desc *si;
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uint64_t pcibase;
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int domain, node, irt, irq, flags, devoffset, num;
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uint16_t devid;
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domain = pcib_get_domain(dev);
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node = s / 8;
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devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f);
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if (!nlm_dev_exists(devoffset))
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return;
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/* Find if there is a desc for the SoC device */
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devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2);
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si = xlp_find_soc_desc(devid);
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/* update flags and irq from desc if available */
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irq = 0;
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flags = 0;
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if (si != NULL) {
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if (si->irqbase != 0)
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irq = si->irqbase + si->ndevs;
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flags = si->flags;
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si->ndevs++;
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}
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/* skip internal devices */
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if ((flags & INTERNAL_DEV) != 0)
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return;
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/* PCIe interfaces are special, bug in Ax */
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if (devid == PCI_DEVICE_ID_NLM_PCIE) {
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xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f);
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} else {
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/* Stash intline and pin in shadow reg for devices */
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pcibase = nlm_pcicfg_base(devoffset);
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irt = nlm_irtstart(pcibase);
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num = nlm_irtnum(pcibase);
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if (irq != 0 && num > 0) {
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xlp_add_irq(node, irt, irq);
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nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0,
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(1 << 8) | irq);
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}
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}
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dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo));
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if (dinfo == NULL)
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return;
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xlp_dinfo = (struct xlp_devinfo *)dinfo;
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xlp_dinfo->irq = irq;
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xlp_dinfo->flags = flags;
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/* memory resource from ecfg space, if MEM_RES_EMUL is set */
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if ((flags & MEM_RES_EMUL) != 0)
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xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset +
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XLP_IO_PCI_HDRSZ;
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pci_add_child(dev, dinfo);
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}
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static int
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xlp_pci_attach(device_t dev)
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{
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device_t pcib = device_get_parent(dev);
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int maxslots, s, f, pcifunchigh;
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int busno;
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uint8_t hdrtype;
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/*
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* The on-chip devices are on a bus that is almost, but not
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* quite, completely like PCI. Add those things by hand.
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*/
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busno = pcib_get_bus(dev);
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maxslots = PCIB_MAXSLOTS(pcib);
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for (s = 0; s <= maxslots; s++) {
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pcifunchigh = 0;
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f = 0;
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hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (hdrtype & PCIM_MFDEV)
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pcifunchigh = PCI_FUNCMAX;
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for (f = 0; f <= pcifunchigh; f++)
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xlp_add_soc_child(pcib, dev, busno, s, f);
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}
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return (bus_generic_attach(dev));
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}
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static int
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xlp_pci_probe(device_t dev)
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{
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device_t pcib;
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pcib = device_get_parent(dev);
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/*
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* Only the top level bus has SoC devices, leave the rest to
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* Generic PCI code
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*/
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if (strcmp(device_get_nameunit(pcib), "pcib0") != 0)
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return (ENXIO);
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device_set_desc(dev, "XLP SoCbus");
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return (BUS_PROBE_DEFAULT);
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}
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static devclass_t pci_devclass;
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static device_method_t xlp_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, xlp_pci_probe),
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DEVMETHOD(device_attach, xlp_pci_attach),
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DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource),
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DEVMETHOD(bus_release_resource, xlp_pci_release_resource),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc),
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pci_driver);
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DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0);
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static devclass_t pcib_devclass;
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static struct rman irq_rman, port_rman, mem_rman, emul_rman;
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static void
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xlp_pcib_init_resources(void)
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{
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irq_rman.rm_start = 0;
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irq_rman.rm_end = 255;
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irq_rman.rm_type = RMAN_ARRAY;
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irq_rman.rm_descr = "PCI Mapped Interrupts";
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if (rman_init(&irq_rman)
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|| rman_manage_region(&irq_rman, 0, 255))
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panic("pci_init_resources irq_rman");
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port_rman.rm_start = 0;
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port_rman.rm_end = ~0ul;
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port_rman.rm_type = RMAN_ARRAY;
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port_rman.rm_descr = "I/O ports";
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if (rman_init(&port_rman)
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|| rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT))
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panic("pci_init_resources port_rman");
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mem_rman.rm_start = 0;
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mem_rman.rm_end = ~0ul;
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mem_rman.rm_type = RMAN_ARRAY;
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mem_rman.rm_descr = "I/O memory";
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if (rman_init(&mem_rman)
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|| rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT))
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panic("pci_init_resources mem_rman");
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/*
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* This includes the GBU (nor flash) memory range and the PCIe
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* memory area.
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*/
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emul_rman.rm_start = 0;
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emul_rman.rm_end = ~0ul;
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emul_rman.rm_type = RMAN_ARRAY;
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emul_rman.rm_descr = "Emulated MEMIO";
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if (rman_init(&emul_rman)
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|| rman_manage_region(&emul_rman, EMUL_MEM_START, EMUL_MEM_END))
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panic("pci_init_resources emul_rman");
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}
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static int
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xlp_pcib_probe(device_t dev)
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{
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device_set_desc(dev, "XLP PCI bus");
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xlp_pcib_init_resources();
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return (0);
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}
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static int
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xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = 0;
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return (0);
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}
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return (ENOENT);
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}
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|
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static int
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xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
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{
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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return (EINVAL);
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case PCIB_IVAR_BUS:
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return (EINVAL);
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}
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return (ENOENT);
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}
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|
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static int
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xlp_pcib_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static u_int32_t
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xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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uint32_t data = 0;
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uint64_t cfgaddr;
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int regindex = reg/sizeof(uint32_t);
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cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
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if ((width == 2) && (reg & 1))
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return 0xFFFFFFFF;
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else if ((width == 4) && (reg & 3))
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return 0xFFFFFFFF;
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|
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/*
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* The intline and int pin of SoC devices are DOA, except
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* for bridges (slot %8 == 1).
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* use the values we stashed in a writable PCI scratch reg.
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*/
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if (b == 0 && regindex == 0xf && s % 8 > 1)
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regindex = XLP_PCI_DEVSCRATCH_REG0;
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data = nlm_read_pci_reg(cfgaddr, regindex);
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if (width == 1)
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return ((data >> ((reg & 3) << 3)) & 0xff);
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else if (width == 2)
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return ((data >> ((reg & 3) << 3)) & 0xffff);
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else
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return (data);
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}
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|
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static void
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xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
|
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u_int reg, u_int32_t val, int width)
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{
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uint64_t cfgaddr;
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uint32_t data = 0;
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int regindex = reg / sizeof(uint32_t);
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cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
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if ((width == 2) && (reg & 1))
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return;
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else if ((width == 4) && (reg & 3))
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return;
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|
|
if (width == 1) {
|
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data = nlm_read_pci_reg(cfgaddr, regindex);
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data = (data & ~(0xff << ((reg & 3) << 3))) |
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(val << ((reg & 3) << 3));
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} else if (width == 2) {
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data = nlm_read_pci_reg(cfgaddr, regindex);
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data = (data & ~(0xffff << ((reg & 3) << 3))) |
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(val << ((reg & 3) << 3));
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} else {
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data = val;
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}
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|
|
/*
|
|
* use shadow reg for intpin/intline which are dead
|
|
*/
|
|
if (b == 0 && regindex == 0xf && s % 8 > 1)
|
|
regindex = XLP_PCI_DEVSCRATCH_REG0;
|
|
nlm_write_pci_reg(cfgaddr, regindex, data);
|
|
}
|
|
|
|
/*
|
|
* Enable byte swap in hardware. Program a link's PCIe SWAP regions
|
|
* from the link's IO and MEM address ranges.
|
|
*/
|
|
static void
|
|
xlp_pcib_hardware_swap_enable(int node, int link)
|
|
{
|
|
uint64_t bbase, linkpcibase;
|
|
uint32_t bar;
|
|
int pcieoffset;
|
|
|
|
pcieoffset = XLP_IO_PCIE_OFFSET(node, link);
|
|
if (!nlm_dev_exists(pcieoffset))
|
|
return;
|
|
|
|
bbase = nlm_get_bridge_regbase(node);
|
|
linkpcibase = nlm_pcicfg_base(pcieoffset);
|
|
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link);
|
|
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
|
|
|
|
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
|
|
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
|
|
|
|
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
|
|
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
|
|
|
|
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
|
|
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
|
|
}
|
|
|
|
static int
|
|
xlp_pcib_attach(device_t dev)
|
|
{
|
|
int node, link;
|
|
|
|
/* enable hardware swap on all nodes/links */
|
|
for (node = 0; node < XLP_MAX_NODES; node++)
|
|
for (link = 0; link < 4; link++)
|
|
xlp_pcib_hardware_swap_enable(node, link);
|
|
|
|
device_add_child(dev, "pci", 0);
|
|
bus_generic_attach(dev);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
xlp_pcib_identify(driver_t * driver, device_t parent)
|
|
{
|
|
|
|
BUS_ADD_CHILD(parent, 0, "pcib", 0);
|
|
}
|
|
|
|
/*
|
|
* XLS PCIe can have upto 4 links, and each link has its on IRQ
|
|
* Find the link on which the device is on
|
|
*/
|
|
static int
|
|
xlp_pcie_link(device_t pcib, device_t dev)
|
|
{
|
|
device_t parent, tmp;
|
|
|
|
/* find the lane on which the slot is connected to */
|
|
tmp = dev;
|
|
while (1) {
|
|
parent = device_get_parent(tmp);
|
|
if (parent == NULL || parent == pcib) {
|
|
device_printf(dev, "Cannot find parent bus\n");
|
|
return (-1);
|
|
}
|
|
if (strcmp(device_get_nameunit(parent), "pci0") == 0)
|
|
break;
|
|
tmp = parent;
|
|
}
|
|
return (pci_get_function(tmp));
|
|
}
|
|
|
|
static int
|
|
xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
|
|
{
|
|
int i, link;
|
|
|
|
/*
|
|
* Each link has 32 MSIs that can be allocated, but for now
|
|
* we only support one device per link.
|
|
* msi_alloc() equivalent is needed when we start supporting
|
|
* bridges on the PCIe link.
|
|
*/
|
|
link = xlp_pcie_link(pcib, dev);
|
|
if (link == -1)
|
|
return (ENXIO);
|
|
|
|
/*
|
|
* encode the irq so that we know it is a MSI interrupt when we
|
|
* setup interrupts
|
|
*/
|
|
for (i = 0; i < count; i++)
|
|
irqs[i] = 64 + link * 32 + i;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
|
|
uint32_t *data)
|
|
{
|
|
int msi, irt;
|
|
|
|
if (irq >= 64) {
|
|
msi = irq - 64;
|
|
*addr = MIPS_MSI_ADDR(0);
|
|
|
|
irt = xlp_pcie_link_irt(msi/32);
|
|
if (irt != -1)
|
|
*data = MIPS_MSI_DATA(xlp_irt_to_irq(irt));
|
|
return (0);
|
|
} else {
|
|
device_printf(dev, "%s: map_msi for irq %d - ignored",
|
|
device_get_nameunit(pcib), irq);
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
static void
|
|
bridge_pcie_ack(int irq)
|
|
{
|
|
uint32_t node,reg;
|
|
uint64_t base;
|
|
|
|
node = nlm_nodeid();
|
|
reg = PCIE_MSI_STATUS;
|
|
|
|
switch (irq) {
|
|
case PIC_PCIE_0_IRQ:
|
|
base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node));
|
|
break;
|
|
case PIC_PCIE_1_IRQ:
|
|
base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node));
|
|
break;
|
|
case PIC_PCIE_2_IRQ:
|
|
base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node));
|
|
break;
|
|
case PIC_PCIE_3_IRQ:
|
|
base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node));
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
nlm_write_pci_reg(base, reg, 0xFFFFFFFF);
|
|
return;
|
|
}
|
|
|
|
static int
|
|
mips_platform_pcib_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq, int flags, driver_filter_t *filt,
|
|
driver_intr_t *intr, void *arg, void **cookiep)
|
|
{
|
|
int error = 0;
|
|
int xlpirq;
|
|
void *extra_ack;
|
|
|
|
error = rman_activate_resource(irq);
|
|
if (error)
|
|
return error;
|
|
if (rman_get_start(irq) != rman_get_end(irq)) {
|
|
device_printf(dev, "Interrupt allocation %lu != %lu\n",
|
|
rman_get_start(irq), rman_get_end(irq));
|
|
return (EINVAL);
|
|
}
|
|
xlpirq = rman_get_start(irq);
|
|
if (xlpirq == 0)
|
|
return (0);
|
|
|
|
if (strcmp(device_get_name(dev), "pcib") != 0)
|
|
return (0);
|
|
|
|
/*
|
|
* temporary hack for MSI, we support just one device per
|
|
* link, and assign the link interrupt to the device interrupt
|
|
*/
|
|
if (xlpirq >= 64) {
|
|
int node, val, link;
|
|
uint64_t base;
|
|
|
|
xlpirq -= 64;
|
|
if (xlpirq % 32 != 0)
|
|
return (0);
|
|
|
|
node = nlm_nodeid();
|
|
link = xlpirq / 32;
|
|
base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link));
|
|
|
|
/* MSI Interrupt Vector enable at bridge's configuration */
|
|
nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN);
|
|
|
|
val = nlm_read_pci_reg(base, PCIE_INT_EN0);
|
|
/* MSI Interrupt enable at bridge's configuration */
|
|
nlm_write_pci_reg(base, PCIE_INT_EN0,
|
|
(val | PCIE_MSI_INT_EN));
|
|
|
|
/* legacy interrupt disable at bridge */
|
|
val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD);
|
|
nlm_write_pci_reg(base, PCIE_BRIDGE_CMD,
|
|
(val | PCIM_CMD_INTxDIS));
|
|
|
|
/* MSI address update at bridge */
|
|
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL,
|
|
MSI_MIPS_ADDR_BASE);
|
|
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0);
|
|
|
|
val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP);
|
|
/* MSI capability enable at bridge */
|
|
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
|
|
(val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
|
|
(PCIM_MSICTRL_MMC_32 << 16)));
|
|
|
|
xlpirq = xlp_pcie_link_irt(xlpirq / 32);
|
|
if (xlpirq == -1)
|
|
return (EINVAL);
|
|
xlpirq = xlp_irt_to_irq(xlpirq);
|
|
}
|
|
/* Set all irqs to CPU 0 for now */
|
|
nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0,
|
|
PIC_LOCAL_SCHEDULING, xlpirq, 0);
|
|
extra_ack = NULL;
|
|
if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ)
|
|
extra_ack = bridge_pcie_ack;
|
|
xlp_establish_intr(device_get_name(child), filt,
|
|
intr, arg, xlpirq, flags, cookiep, extra_ack);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mips_platform_pcib_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
if (strcmp(device_get_name(child), "pci") == 0) {
|
|
/* if needed reprogram the pic to clear pcix related entry */
|
|
device_printf(dev, "teardown intr\n");
|
|
}
|
|
return (bus_generic_teardown_intr(dev, child, irq, cookie));
|
|
}
|
|
|
|
static struct resource *
|
|
xlp_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
|
u_long start, u_long end, u_long count, u_int flags)
|
|
{
|
|
struct rman *rm = NULL;
|
|
struct resource *rv;
|
|
void *va;
|
|
int needactivate = flags & RF_ACTIVE;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IRQ:
|
|
rm = &irq_rman;
|
|
break;
|
|
|
|
case SYS_RES_IOPORT:
|
|
rm = &port_rman;
|
|
break;
|
|
|
|
case SYS_RES_MEMORY:
|
|
if (start >= EMUL_MEM_START && start <= EMUL_MEM_END)
|
|
rm = &emul_rman;
|
|
else
|
|
rm = &mem_rman;
|
|
break;
|
|
|
|
default:
|
|
return (0);
|
|
}
|
|
|
|
rv = rman_reserve_resource(rm, start, end, count, flags, child);
|
|
if (rv == NULL)
|
|
return (NULL);
|
|
|
|
rman_set_rid(rv, *rid);
|
|
|
|
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
|
|
va = pmap_mapdev(start, count);
|
|
rman_set_bushandle(rv, (bus_space_handle_t)va);
|
|
rman_set_bustag(rv, rmi_bus_space);
|
|
}
|
|
if (needactivate) {
|
|
if (bus_activate_resource(child, type, *rid, rv)) {
|
|
rman_release_resource(rv);
|
|
return (NULL);
|
|
}
|
|
}
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
xlp_pcib_release_resource(device_t bus, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
|
|
return (rman_release_resource(r));
|
|
}
|
|
|
|
static int
|
|
xlp_pcib_activate_resource(device_t bus, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
|
|
return (rman_activate_resource(r));
|
|
}
|
|
|
|
static int
|
|
xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
|
|
return (rman_deactivate_resource(r));
|
|
}
|
|
|
|
static int
|
|
mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
|
|
{
|
|
int irt, link;
|
|
|
|
/*
|
|
* Validate requested pin number.
|
|
*/
|
|
if ((pin < 1) || (pin > 4))
|
|
return (255);
|
|
|
|
if (pci_get_bus(dev) == 0 &&
|
|
pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) {
|
|
/* SoC devices */
|
|
uint64_t pcibase;
|
|
int f, n, d, num;
|
|
|
|
f = pci_get_function(dev);
|
|
n = pci_get_slot(dev) / 8;
|
|
d = pci_get_slot(dev) % 8;
|
|
|
|
/*
|
|
* For PCIe links, return link IRT, for other SoC devices
|
|
* get the IRT from its PCIe header
|
|
*/
|
|
if (d == 1) {
|
|
irt = xlp_pcie_link_irt(f);
|
|
} else {
|
|
pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f));
|
|
irt = nlm_irtstart(pcibase);
|
|
num = nlm_irtnum(pcibase);
|
|
if (num != 1)
|
|
device_printf(bus, "[%d:%d:%d] Error %d IRQs\n",
|
|
n, d, f, num);
|
|
}
|
|
} else {
|
|
/* Regular PCI devices */
|
|
link = xlp_pcie_link(bus, dev);
|
|
irt = xlp_pcie_link_irt(link);
|
|
}
|
|
|
|
if (irt != -1)
|
|
return (xlp_irt_to_irq(irt));
|
|
|
|
return (255);
|
|
}
|
|
|
|
static device_method_t xlp_pcib_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_identify, xlp_pcib_identify),
|
|
DEVMETHOD(device_probe, xlp_pcib_probe),
|
|
DEVMETHOD(device_attach, xlp_pcib_attach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, xlp_pcib_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, xlp_pcib_release_resource),
|
|
DEVMETHOD(bus_activate_resource, xlp_pcib_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, xlp_pcib_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots),
|
|
DEVMETHOD(pcib_read_config, xlp_pcib_read_config),
|
|
DEVMETHOD(pcib_write_config, xlp_pcib_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt),
|
|
|
|
DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, xlp_release_msi),
|
|
DEVMETHOD(pcib_map_msi, xlp_map_msi),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t xlp_pcib_driver = {
|
|
"pcib",
|
|
xlp_pcib_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0);
|