5b03aba6c8
files to vendor-provided ones. It should make easier to adopt platform code to new revisions of hardware and to use DTS overlays for various Beaglebone extensions (shields/capes). Original dts filenames were not changed, they're now wrappers over dts files provided by TI. So make sure you update .dtb files on your devices as part of kernel update GPIO addressing was changed: instead of one global /dev/gpioc0 there are per-bank instances of /dev/gpiocX. Each bank has 32 pins so for instance pin 121 on /dev/gpioc0 in old addressing scheme is now pin 25 on /dev/gpioc3 On Pandaboard serial console devices was changed from /dev/ttyu0 to /dev/ttyu2 so you'll have to update /etc/ttys to get login prompt on serial port in multiuser mode. Single user mode serial console should work as-is Differential Revision: https://reviews.freebsd.org/D2146 Reviewed by: rpaulo, ian, Michal Meloun, Svatopluk Kraus
467 lines
14 KiB
C
467 lines
14 KiB
C
/*-
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* Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/rman.h>
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#include <sys/module.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <arm/ti/ti_prcm.h>
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#include <arm/ti/usb/omap_usb.h>
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/*
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* USB Host Module
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*/
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/* UHH */
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#define OMAP_USBHOST_UHH_REVISION 0x0000
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#define OMAP_USBHOST_UHH_SYSCONFIG 0x0010
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#define OMAP_USBHOST_UHH_SYSSTATUS 0x0014
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#define OMAP_USBHOST_UHH_HOSTCONFIG 0x0040
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#define OMAP_USBHOST_UHH_DEBUG_CSR 0x0044
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/* UHH Register Set */
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#define UHH_SYSCONFIG_MIDLEMODE_MASK (3UL << 12)
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#define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY (2UL << 12)
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#define UHH_SYSCONFIG_MIDLEMODE_NOSTANDBY (1UL << 12)
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#define UHH_SYSCONFIG_MIDLEMODE_FORCESTANDBY (0UL << 12)
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#define UHH_SYSCONFIG_CLOCKACTIVITY (1UL << 8)
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#define UHH_SYSCONFIG_SIDLEMODE_MASK (3UL << 3)
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#define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE (2UL << 3)
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#define UHH_SYSCONFIG_SIDLEMODE_NOIDLE (1UL << 3)
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#define UHH_SYSCONFIG_SIDLEMODE_FORCEIDLE (0UL << 3)
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#define UHH_SYSCONFIG_ENAWAKEUP (1UL << 2)
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#define UHH_SYSCONFIG_SOFTRESET (1UL << 1)
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#define UHH_SYSCONFIG_AUTOIDLE (1UL << 0)
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#define UHH_HOSTCONFIG_APP_START_CLK (1UL << 31)
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#define UHH_HOSTCONFIG_P3_CONNECT_STATUS (1UL << 10)
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#define UHH_HOSTCONFIG_P2_CONNECT_STATUS (1UL << 9)
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#define UHH_HOSTCONFIG_P1_CONNECT_STATUS (1UL << 8)
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#define UHH_HOSTCONFIG_ENA_INCR_ALIGN (1UL << 5)
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#define UHH_HOSTCONFIG_ENA_INCR16 (1UL << 4)
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#define UHH_HOSTCONFIG_ENA_INCR8 (1UL << 3)
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#define UHH_HOSTCONFIG_ENA_INCR4 (1UL << 2)
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#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN (1UL << 1)
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#define UHH_HOSTCONFIG_P1_ULPI_BYPASS (1UL << 0)
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/* The following are on rev2 (OMAP44xx) of the EHCI only */
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#define UHH_SYSCONFIG_IDLEMODE_MASK (3UL << 2)
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#define UHH_SYSCONFIG_IDLEMODE_NOIDLE (1UL << 2)
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#define UHH_SYSCONFIG_STANDBYMODE_MASK (3UL << 4)
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#define UHH_SYSCONFIG_STANDBYMODE_NOSTDBY (1UL << 4)
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#define UHH_HOSTCONFIG_P1_MODE_MASK (3UL << 16)
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#define UHH_HOSTCONFIG_P1_MODE_ULPI_PHY (0UL << 16)
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#define UHH_HOSTCONFIG_P1_MODE_UTMI_PHY (1UL << 16)
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#define UHH_HOSTCONFIG_P1_MODE_HSIC (3UL << 16)
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#define UHH_HOSTCONFIG_P2_MODE_MASK (3UL << 18)
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#define UHH_HOSTCONFIG_P2_MODE_ULPI_PHY (0UL << 18)
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#define UHH_HOSTCONFIG_P2_MODE_UTMI_PHY (1UL << 18)
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#define UHH_HOSTCONFIG_P2_MODE_HSIC (3UL << 18)
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/*
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* Values of UHH_REVISION - Note: these are not given in the TRM but taken
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* from the linux OMAP EHCI driver (thanks guys). It has been verified on
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* a Panda and Beagle board.
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*/
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#define OMAP_UHH_REV1 0x00000010 /* OMAP3 */
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#define OMAP_UHH_REV2 0x50700100 /* OMAP4 */
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struct omap_uhh_softc {
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struct simplebus_softc simplebus_sc;
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device_t sc_dev;
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/* UHH register set */
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struct resource* uhh_mem_res;
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/* The revision of the HS USB HOST read from UHH_REVISION */
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uint32_t uhh_rev;
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/* The following details are provided by conf hints */
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int port_mode[3];
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};
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static device_attach_t omap_uhh_attach;
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static device_detach_t omap_uhh_detach;
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static inline uint32_t
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omap_uhh_read_4(struct omap_uhh_softc *sc, bus_size_t off)
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{
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return bus_read_4(sc->uhh_mem_res, off);
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}
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static inline void
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omap_uhh_write_4(struct omap_uhh_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->uhh_mem_res, off, val);
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}
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static int
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omap_uhh_init(struct omap_uhh_softc *isc)
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{
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uint8_t tll_ch_mask;
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uint32_t reg;
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int i;
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/* Enable Clocks for high speed USBHOST */
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ti_prcm_clk_enable(USBHSHOST_CLK);
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/* Read the UHH revision */
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isc->uhh_rev = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_REVISION);
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device_printf(isc->sc_dev, "UHH revision 0x%08x\n", isc->uhh_rev);
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if (isc->uhh_rev == OMAP_UHH_REV2) {
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/* For OMAP44xx devices you have to enable the per-port clocks:
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* PHY_MODE - External ULPI clock
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* TTL_MODE - Internal UTMI clock
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* HSIC_MODE - Internal 480Mhz and 60Mhz clocks
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*/
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switch(isc->port_mode[0]) {
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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break;
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case EHCI_HCD_OMAP_MODE_PHY:
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if (ti_prcm_clk_set_source(USBP1_PHY_CLK, EXT_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock source for port 0\n");
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if (ti_prcm_clk_enable(USBP1_PHY_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock USBP1_PHY_CLK source for port 0\n");
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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if (ti_prcm_clk_enable(USBP1_UTMI_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock USBP1_PHY_CLK source for port 0\n");
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break;
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case EHCI_HCD_OMAP_MODE_HSIC:
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if (ti_prcm_clk_enable(USBP1_HSIC_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock USBP1_PHY_CLK source for port 0\n");
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break;
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default:
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device_printf(isc->sc_dev, "unknown port mode %d for port 0\n", isc->port_mode[0]);
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}
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switch(isc->port_mode[1]) {
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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break;
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case EHCI_HCD_OMAP_MODE_PHY:
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if (ti_prcm_clk_set_source(USBP2_PHY_CLK, EXT_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock source for port 0\n");
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if (ti_prcm_clk_enable(USBP2_PHY_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock USBP2_PHY_CLK source for port 1\n");
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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if (ti_prcm_clk_enable(USBP2_UTMI_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock USBP2_UTMI_CLK source for port 1\n");
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break;
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case EHCI_HCD_OMAP_MODE_HSIC:
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if (ti_prcm_clk_enable(USBP2_HSIC_CLK))
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device_printf(isc->sc_dev,
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"failed to set clock USBP2_HSIC_CLK source for port 1\n");
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break;
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default:
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device_printf(isc->sc_dev, "unknown port mode %d for port 1\n", isc->port_mode[1]);
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}
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}
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/* Put UHH in SmartIdle/SmartStandby mode */
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reg = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_SYSCONFIG);
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if (isc->uhh_rev == OMAP_UHH_REV1) {
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reg &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK |
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UHH_SYSCONFIG_MIDLEMODE_MASK);
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reg |= (UHH_SYSCONFIG_ENAWAKEUP |
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UHH_SYSCONFIG_AUTOIDLE |
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UHH_SYSCONFIG_CLOCKACTIVITY |
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UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE |
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UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY);
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} else if (isc->uhh_rev == OMAP_UHH_REV2) {
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reg &= ~UHH_SYSCONFIG_IDLEMODE_MASK;
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reg |= UHH_SYSCONFIG_IDLEMODE_NOIDLE;
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reg &= ~UHH_SYSCONFIG_STANDBYMODE_MASK;
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reg |= UHH_SYSCONFIG_STANDBYMODE_NOSTDBY;
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}
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omap_uhh_write_4(isc, OMAP_USBHOST_UHH_SYSCONFIG, reg);
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device_printf(isc->sc_dev, "OMAP_UHH_SYSCONFIG: 0x%08x\n", reg);
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reg = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_HOSTCONFIG);
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/* Setup ULPI bypass and burst configurations */
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reg |= (UHH_HOSTCONFIG_ENA_INCR4 |
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UHH_HOSTCONFIG_ENA_INCR8 |
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UHH_HOSTCONFIG_ENA_INCR16);
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reg &= ~UHH_HOSTCONFIG_ENA_INCR_ALIGN;
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if (isc->uhh_rev == OMAP_UHH_REV1) {
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if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~UHH_HOSTCONFIG_P1_CONNECT_STATUS;
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if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~UHH_HOSTCONFIG_P2_CONNECT_STATUS;
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if (isc->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
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/* Bypass the TLL module for PHY mode operation */
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if ((isc->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
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(isc->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
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(isc->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
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reg &= ~UHH_HOSTCONFIG_P1_ULPI_BYPASS;
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else
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reg |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
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} else if (isc->uhh_rev == OMAP_UHH_REV2) {
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reg |= UHH_HOSTCONFIG_APP_START_CLK;
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/* Clear port mode fields for PHY mode*/
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reg &= ~UHH_HOSTCONFIG_P1_MODE_MASK;
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reg &= ~UHH_HOSTCONFIG_P2_MODE_MASK;
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if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
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reg |= UHH_HOSTCONFIG_P1_MODE_UTMI_PHY;
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else if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_HSIC)
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reg |= UHH_HOSTCONFIG_P1_MODE_HSIC;
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if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
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reg |= UHH_HOSTCONFIG_P2_MODE_UTMI_PHY;
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else if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_HSIC)
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reg |= UHH_HOSTCONFIG_P2_MODE_HSIC;
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}
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omap_uhh_write_4(isc, OMAP_USBHOST_UHH_HOSTCONFIG, reg);
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device_printf(isc->sc_dev, "UHH setup done, uhh_hostconfig=0x%08x\n", reg);
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/* I found the code and comments in the Linux EHCI driver - thanks guys :)
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*
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* "An undocumented "feature" in the OMAP3 EHCI controller, causes suspended
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* ports to be taken out of suspend when the USBCMD.Run/Stop bit is cleared
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* (for example when we do omap_uhh_bus_suspend). This breaks suspend-resume if
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* the root-hub is allowed to suspend. Writing 1 to this undocumented
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* register bit disables this feature and restores normal behavior."
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*/
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#if 0
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omap_uhh_write_4(isc, OMAP_USBHOST_INSNREG04,
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OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND);
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#endif
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tll_ch_mask = 0;
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for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
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if (isc->port_mode[i] == EHCI_HCD_OMAP_MODE_TLL)
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tll_ch_mask |= (1 << i);
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}
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if (tll_ch_mask)
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omap_tll_utmi_enable(tll_ch_mask);
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return(0);
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}
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/**
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* omap_uhh_fini - shutdown the EHCI controller
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* @isc: omap ehci device context
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*
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*
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*
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* LOCKING:
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* none
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*
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* RETURNS:
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* 0 on success, a negative error code on failure.
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*/
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static void
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omap_uhh_fini(struct omap_uhh_softc *isc)
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{
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unsigned long timeout;
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device_printf(isc->sc_dev, "Stopping TI EHCI USB Controller\n");
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/* Set the timeout */
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if (hz < 10)
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timeout = 1;
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else
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timeout = (100 * hz) / 1000;
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/* Reset the UHH, OHCI and EHCI modules */
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omap_uhh_write_4(isc, OMAP_USBHOST_UHH_SYSCONFIG, 0x0002);
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while ((omap_uhh_read_4(isc, OMAP_USBHOST_UHH_SYSSTATUS) & 0x07) == 0x00) {
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/* Sleep for a tick */
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pause("USBRESET", 1);
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if (timeout-- == 0) {
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device_printf(isc->sc_dev, "operation timed out\n");
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break;
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}
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}
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/* Disable functional and interface clocks for the TLL and HOST modules */
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ti_prcm_clk_disable(USBHSHOST_CLK);
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device_printf(isc->sc_dev, "Clock to USB host has been disabled\n");
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}
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int
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omap_usb_port_mode(device_t dev, int port)
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{
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struct omap_uhh_softc *isc;
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isc = device_get_softc(dev);
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if ((port < 0) || (port >= OMAP_HS_USB_PORTS))
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return (-1);
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return isc->port_mode[port];
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}
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static int
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omap_uhh_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ti,usbhs-host"))
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return (ENXIO);
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device_set_desc(dev, "TI OMAP USB 2.0 Host module");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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omap_uhh_attach(device_t dev)
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{
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struct omap_uhh_softc *isc = device_get_softc(dev);
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int err;
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int rid;
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int i;
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phandle_t node;
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char propname[16];
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char *mode;
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/* save the device */
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isc->sc_dev = dev;
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/* Allocate resource for the UHH register set */
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rid = 0;
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isc->uhh_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (!isc->uhh_mem_res) {
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device_printf(dev, "Error: Could not map UHH memory\n");
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goto error;
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}
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node = ofw_bus_get_node(dev);
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if (node == -1)
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goto error;
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/* Get port modes from FDT */
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for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
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isc->port_mode[i] = EHCI_HCD_OMAP_MODE_UNKNOWN;
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snprintf(propname, sizeof(propname),
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"port%d-mode", i+1);
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if (OF_getprop_alloc(node, propname, 1, (void**)&mode) <= 0)
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continue;
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if (strcmp(mode, "ehci-phy") == 0)
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isc->port_mode[i] = EHCI_HCD_OMAP_MODE_PHY;
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else if (strcmp(mode, "ehci-tll") == 0)
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isc->port_mode[i] = EHCI_HCD_OMAP_MODE_TLL;
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else if (strcmp(mode, "ehci-hsic") == 0)
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isc->port_mode[i] = EHCI_HCD_OMAP_MODE_HSIC;
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}
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/* Initialise the ECHI registers */
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err = omap_uhh_init(isc);
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if (err) {
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device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err);
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goto error;
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}
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simplebus_init(dev, node);
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/*
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* Allow devices to identify.
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|
*/
|
|
bus_generic_probe(dev);
|
|
|
|
/*
|
|
* Now walk the OFW tree and attach top-level devices.
|
|
*/
|
|
for (node = OF_child(node); node > 0; node = OF_peer(node))
|
|
simplebus_add_device(dev, node, 0, NULL, -1, NULL);
|
|
return (bus_generic_attach(dev));
|
|
|
|
error:
|
|
omap_uhh_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
omap_uhh_detach(device_t dev)
|
|
{
|
|
struct omap_uhh_softc *isc = device_get_softc(dev);
|
|
|
|
/* during module unload there are lots of children leftover */
|
|
device_delete_children(dev);
|
|
|
|
if (isc->uhh_mem_res) {
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, isc->uhh_mem_res);
|
|
isc->uhh_mem_res = NULL;
|
|
}
|
|
|
|
omap_uhh_fini(isc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t omap_uhh_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, omap_uhh_probe),
|
|
DEVMETHOD(device_attach, omap_uhh_attach),
|
|
DEVMETHOD(device_detach, omap_uhh_detach),
|
|
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_1(omap_uhh, omap_uhh_driver, omap_uhh_methods,
|
|
sizeof(struct omap_uhh_softc), simplebus_driver);
|
|
static devclass_t omap_uhh_devclass;
|
|
DRIVER_MODULE(omap_uhh, simplebus, omap_uhh_driver, omap_uhh_devclass, 0, 0);
|